LIVE WEBINAR: Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM)

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Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM)

Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 18th, 2020

Abstract:

Open Source VHDL Verification Methodology (OSVVM) simplifies and accelerates your FPGA and ASIC verification tasks by providing utility and model (Verification IP) libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. 

This webinar is a guided walk-through of how to create better self-checking tests using OSVVM utility library and OSVVM model independent transactions. 

OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 17% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 30%) leads SystemVerilog+UVM (with 20%). Based on the growth in our training, we expect to see improved numbers in the next survey. 

OSVVM uses a structured, transaction-based test environment – from a high level view the structure is similar to SystemVerilog – although its test harness is structural code, so it is also similar RTL. The similarity to RTL is important. It is what makes OSVVM accessible to RTL as well as verification engineers. 

In this webinar you will learn the OSVVM Way of: 

  • Using OSVVM model independent transactions to facilitate readability and accelerate test construction 
  • Writing tests with concurrent independent actions – just like your models. 
  • Adding Self-Checking to your tests via OSVVM AffirmIf or scoreboards 
  • Adding conditional message printing to facilitate debug and detailed test for reports via OSVVM logs 
  • Adding constrained random to your tests 
  • Using scoreboards for testing 
  • Adding Protocol Checks to your tests using OSVVM Alert 
  • Test Wide Reporting with a count of WARNING, ERROR, FAILURE, and PASSED for each model 
  • Test Synchronization and Watchdogs 

Looking to improve your VHDL FPGA verification methodology? OSVVM is the right solution. We have all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them. 

The OSVVM library now part of the IEEE Open Source effort. You can find us at: https://opensource.ieee.org/osvvm. A mirror of OSVVM libraries are hosted on GitHub at: https://github.com/OSVVM/. 

The presenter, Jim Lewis, is the architect and principal developer of OSVVM. Mr Lewis is also the chair of the IEEE VHDL working group. OSVVM leverages this deep understanding of VHDL to architect a solution that solves difficult problems in a simple way. 

Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses records with unconstrained arrays. We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type. 

[1] https://blogs.mentor.com/verificationhorizons/blog/2019/01/15/part-6-the-2018-wilson-research-group-functional- verification-study/ 

Benefits of OSVVM: 

  • Tests are Readable and Reviewable by All (Hardware, Verification, Software, and System Engineers) 
  • RTL designers can write Tests and/or Models 
  • Reuse and/or upgrade your current VHDL testbench and models 
  • OSVVM is modular – use the pieces you need now. 
  • Supports mixed test approaches (directed, algorithmic, file, constrained random, ...) 
  • Same simple approach used for either small FPGAs or complex ASICs 

Agenda: 

  • 50 min presentation/live demo
  • 10 min Q&A
Event Info                                                                 
EU Session
 3:00 PM – 4:00 PM CEST
 Thursday, June 18, 2020
Register for EU Session
US Session
 11:00 AM – 12:00 PM PDT
 Thursday, June 18, 2020
Register for US Session
Presenter                                                                 
Jim  Lewis

Bio:

Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr Lewis is a founding member of the Open Source VHDL Verification Methodology (OSVVM) and the principal architect of its packages and methodology. Mr. Lewis, who holds a BSEE, BSCEE, and MSEE from Purdue University, serves as chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG).

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Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

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