Henderson, NV – July 15, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, is presenting RISC-V Verification Methodologies and Solutions at the 2020 Virtual Design Automation Conference (DAC) on July 20-24, 2020.
“As the whole world deals with the first year’s impact of COVID-19, we remained focused on our goals and prepared forward looking verification solutions for the biggest stage of the Electronic Design Automation (EDA) industry,” said Louie De Luna, Director of Marketing. “The EDA has been a huge cornerstone of the digital revolution and technological progress we have achieved as a society during these past few decades, and we are honored to have been a pioneer since 1984. Within the next decade amid the pandemic, the EDA and semiconductor industry face an even greater undertaking to enable IoT, 5G and AI as they become more intertwined with our society to improve our daily lives. A transformation in CPU design and architecture is needed to support a diverse set of future computational workloads, and we believe that a free and open-source Instruction Set Architecture (ISA) can be a solid stepping stone to achieve this transformation. In this year’s DAC, we are officially joining the RISC-V revolution showcasing our hardware verification technologies in the areas of RTL simulation, static verification, FPGA-based emulation and prototyping. Aldec’s verification technology will play a critical role in enabling the industry verify RISC-V based designs efficiently with the highest degree of accuracy.”
Demonstrations all week
The following presentations will be offered continuously throughout the three main days of DAC – July 20, 21 and 22 from 10:30 AM – 1:30 PM US Pacific Time Zone.
Each presentation will last about 30 minutes and interested parties are advised to pre-register and select their preferred subject matter and to secure their preferred date and time slot.
Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores Read more
UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV Read more
Static Verification for RISC-V Cores and SoCs Read more
RISC-V Design & Verification with FPGA Hardware In The Loop Read more
PCIe 5.0 IP + VIP UVM Simulation Environment Read more
System-on-Chip Design In-Circuit Emulation with External PCI Express Devices Read more
Contact Email Contact or call +1(702) 990-4400 for more details.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic System Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design. www.dac.com
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com