Symbiotic EDA Selects Verific Parser Platform as Front End to SoC Synthesis, Formal Verification, FPGA Chip Design Software

Commends Verific for Superior Support that Stands Head and Shoulders Above Others

ALAMEDA, CALIF. –– September 15, 2020 –– Verific Design Automation today confirmed its Parser Platform serves as the front end to Symbiotic EDA’s system-on-chip (SoC) synthesis, formal verification and field programmable gate array (FPGA) chip design software.

Symbiotic EDA, noted for reducing risk in chip design and hardware manufacturing, has used Verific’s SystemVerilog and VHDL parsers and its static and register transfer level (RTL) elaborators since 2018. “We credit Verific with broadening the robustness of our tool suite and helping us ensure our tools are compatible with industry standards,” remarks Claire Wolf, Symbiotic EDA’s founder and chief technology officer. “Verific provides sophisticated and high-quality software strengthened through years of development and actual customer use. Perhaps, it’s Verific’s superior support that is most commendable. Verific truly stands head and shoulders above the rest, as its tagline states”

Michiel Ligthart, president and chief operating officer of Verific, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, is equally enthusiastic. “The breadth of the Symbiotic EDA suite offers solutions for a variety of needs. Symbiotic EDA is a creative chip design verification software supplier developing tools to enable real innovation in our industry. We are glad to play a part in its success.”

In addition, Verific and Symbiotic EDA partner on a no-cost program for educational institutions, providing an executable version of the open-source tool Yosys extended with Verific's SystemVerilog and VHDL parsers.

Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.

About Symbiotic EDA

Symbiotic EDA, a supplier of formal verification and FPGA design tools that reduce risk in the chip design and hardware manufacturing industry, is based in Vienna, Austria. The Symbiotic EDA Suite is a collection of software packages for the design of digital circuits to improve productivity, accelerate design writing and refactoring, ease defect discovery and increase confidence in design functionality. Learn more at:

About Verific Design Automation

Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

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Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact


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