LIVE WEBINAR: High-Performance PCIe 5.0 IP + VIP UVM Verification Environment

Aldec Logo
 
         
Live
                                                                                                                                                                                        Webinar

High-Performance PCIe 5.0 IP + VIP UVM Verification Environment

Presenters: Michal Pacula, Technical Support Manager, Aldec
Sampath Banka, Sr. Applications Engineer, PLDA
Florentin BOSSHARD, Verification Engineer, PLDA
Luis E. Rodriguez, Verification IP Solutions Manager, Avery
Thursday, October 15, 2020

Abstract:

Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically adjustable application clock frequency and clock/power gating. Avery’s APCIe-Xactor includes best-in-class Verification IP for PCIe GEN5, native SystemVerilog and UVM support, native randomization, layer wise protocol and debug tracker and 35+ callbacks for error injection. In Aldec’s Riviera-PRO you can run RTL simulation and debug, visualize simulation waveforms, view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections, and as well as use code coverage to analyze the efficiency of the UVM tests for exercising various parts of the RTL code.

 

Agenda: 

  • PLDA’s PCIe 5.0 XpressRich IP
  • Avery’s APCIe-Xactor VIP
  • UVM-based simulation with Riviera-PRO
  • Conclusion
  • Q&A
Event Info                                                                 
EU Session
 3:00 PM – 4:00 PM CEST
 Thursday, October 15, 2020
Register for EU Session
US Session
 11:00 AM – 12:00 PM PT
 Thursday, October 15, 2020
Register for US Session
Presenter and Authors                                                                 
Michal  Pacula

Michal Pacula, Technical Support Manager, Aldec

Michal joined Aldec in 1998 and worked in a wide range of positions that include Application Engineer and SQA Manager responsible for Active-CAD, Active-HDL and Riviera-PRO products.  Michal’s practical experience includes Digital Design, Verification Methodologies and a deep understanding of HDL modeling. Michal graduated with M.S. in Electronic Engineering (EE) at the Silesian University of Technology in Gliwice, Poland.

Sampath  Banka

Sampath Banka, Sr. Applications Engineer, PLDA

Sampath has over 12 years of experience in Design & Verification and over 7 years of experience in PCI Express IP cores Integration, Debug and Verification. He has worked with PLDA's customers and PHY partners worldwide to help them with PHY interoperability, integration and debugging of PCIe Express based designs. Sampath holds a B.E in Electronics and Communications Engineering from Anna University, India and PGDVLSI from TIIT, San Jose.

Florentin  Bosshard

Florentin Bosshard, Verification Engineer, PLDA

Florentin has been working at PLDA – High speed interconnect leader – for over 2 years now, as verification engineer. As responsible for verification of the PLDA PCIe IP product, he uses and develops several verification environments, including internal and VIP-based. He received his engineering degree in electronics and computer science from Polytech Grenoble, France.

Luis
                                                                                                                                                                                        Rodriguez

Luis E. Rodriguez, Verification IP Solutions Manager, Avery

Over the past 15 years Luis has held roles in R&D development, managing teams as well as in customer facing projects and business development. He has worked on PCIe related products for most of his career, and participates in industry events and consortiums. He is currently chairing a subgroup of the CXL Compliance Workgroup.

View On Demand Webinar
View Upcoming Webinars

Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

Aldec
                                                                                                                                                                                        Logo
 
 
 

For more product information, please contact  sales@aldec.com  or your  local distributor .

Aldec, Inc.
2260 Corporate Circle, Henderson, NV 89074, USA
+702.990.4400 | www.aldec.com




Review Article Be the first to review this article
Aldec


Featured Video
Jobs
Entry Level Design Verification Engineer for Cirrus Logic, Inc. at Austin, Texas
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
ASIC Engineer for Amazon at seattle, Washington
Technical Marketing Mmanager for EDA Careers at Fremont, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Upcoming Events
Si2 AI/ML Winter Workshop at United States - Jan 29, 2021
virtual DATE 2021 at France - Feb 1 - 5, 2021
SEMI Technology Unites Global Summit at United States - Feb 15 - 19, 2021
DVCon U.S. 2021 at Virtual - Mar 1 - 4, 2021
Verific: SystemVerilog & VHDL Parsers
TrueCircuits:



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise