Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts

Samsung and Cadence collaborate to deliver an integrated flow for designing the next generation of automotive, mobile, data center, artificial intelligence (AI) and other emerging applications

SAN JOSE, Calif. — (BUSINESS WIRE) — October 28, 2020 — Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 3nm GAA process technology for early design starts. The certification ensures mutual customers of Cadence and Samsung Foundry have immediate access to a highly automated circuit design, layout, signoff and verification flow to efficiently design products for automotive, mobile, data center, artificial intelligence (AI) and other emerging applications at 3nm.

The automated Cadence® custom and AMS full flow supports the company’s Intelligent System Design strategy, enabling SoC design excellence. For more information on the Cadence custom and AMS flow that supports the Samsung 3nm process technology, visit www.cadence.com/go/CadenceSamsungAMS3nm.

When designing for the 3nm GAA process, the Cadence Virtuoso® layout flow provides a high level of automation and integration, enabling faster design closure with reduced numbers of iterations. The Cadence tools in the flow incorporate key features that are well suited for digitally assisted analog designs such as high performance, best-in-class analysis and verification capabilities developed in the Cadence Spectre® Accelerated Parallel Simulator (APS). In addition, the Innovus Implementation System and the Cadence digital suite are enabled for the Samsung 3nm process node, allowing customers to implement larger, more complex digital blocks.

The complete, certified custom and AMS flow includes the Virtuoso ADE Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre X Simulator, Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), LDE Electrical Analyzer (LEA), Innovus Implementation System, and Pegasus Verification System. Key technical capabilities include:

  • Schematic migration: Allows automated migration using the Cadence Virtuoso Automated Layout Enhancer framework
  • Circuit design and verification: Lets users verify circuit performance and reliability by performing static and dynamic circuit checks, DC/TRAN/C/STB corner simulation, transient noise simulation, Monte Carlo simulation and high-yield estimation, periodic steady state (PSS), periodic small-signal (PNOISE), aging and IR drop and electromigration (EM-IR) analysis
  • Analog layout: Provides improved productivity via automated constraint-driven, row-based device placement and routing with support for width spacing patterns (WSPs), automated routing with WSPs and pin-to-trunk features, EAD to achieve electrically correct designs with reduced iterations, DRC verification during layout using the signoff deck and the Pegasus Verification System’s interactive capabilities, and automated digital block implementation
  • Physical verification and signoff: Offers post-layout simulation in Spectre X Simulator using Quantus extracted parasitics in detailed standard parasitic format (DSPF), full-chip DRC, layout versus schematic (LVS) signoff and color decomposition using Pegasus verification, and DFM pattern matching check using LPA for detecting and correcting process hot spots and improving yields
  • Custom digital and P&R digital layout: Enables seamless interoperability between the Virtuoso platform and Innovus Implementation because the process design kit (PDK) techfile is mixed-signal OpenAccess-ready. For digital block implementation using custom digital methodology, after power mesh using WSP Power Routing (WPR) in the Virtuoso platform and automated row-based standard cell placement using the Virtuoso custom placer, the design is taken into Innovus Implementation for digital routing. The pure digital block can be entirely implemented in Innovus Implementation and brought back into the Virtuoso platform for integration.

“We have validated the Cadence AMS tools along with the entire flow, and it meets our requirements for designing with 3nm GAA process technology,” said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics. “This high-performance flow is available immediately to our customers and represents a major milestone in our ongoing collaboration with Cadence. This additional step provides our customers with advanced design capabilities to improve productivity and fulfill market challenges.”

“In collaboration with Samsung, we’ve achieved certification for our integrated AMS flow at 3nm GAA to drive continued advancements with next-generation design work,” said KT Moore, vice president, product management in the Custom IC and PCB Group at Cadence. “Based on our leading Virtuoso and Spectre platforms, the flow enables highly efficient AMS designs so our mutual customers can quickly complete complex 3nm designs to meet the needs of evolving end-markets, including automotive, AI, and 5G.”

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.



Contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com




Review Article Be the first to review this article
Aldec


Featured Video
Editorial
More Editorial  
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
Focus a Global Reseller Channel on Your Product
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Functional Safety and Security in Embedded Systems
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Phil Kaufman Award Goes on Hiatus for 2020
Colin WallsEmbedded Software
by Colin Walls
Why develop embedded software bottom up?
Jobs
ASIC Design Engineer, for Apple Inc at Cupertino, California
ASIC Design Integration Engineer for Apple Inc at Cupertino, California
Technical Marketing Mmanager for EDA Careers at Fremont, California
Senior Application Engineer Formal Verification for EDA Careers at California or Austin, California
Product Line Manager for EDA Careers at Multiple, North Carolina
ASIC Engineer for Amazon at seattle, Washington
Upcoming Events
RISC-V Summit 2020. at United States - Dec 7 - 10, 2020
SEMICON Japan 2020 Goes Virtual at Japan - Dec 11 - 18, 2020
virtual DATE 2021 at France - Feb 1 - 5, 2021
IPC APEX EXPO 2021 at San Diego Convention Center san diego - Mar 6 - 11, 2021
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits:



© 2020 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise