Live Webinar: Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC

Presenter: Ernst Wehlage, PLC2 GmbH Germany, Xilinx authorized training partner
Thursday, December 3, 2020

Event Info                                                                 
EU Session
 3:00 PM – 4:00 PM CET
 Thursday, December 3, 2020
Register for EU Session
US Session
 11:00 AM – 12:00 PM PST
 Thursday, December 3, 2020
Register for US Session
Presenter                                                                 
Ernst
                                                                                                                    Wehlage

Bio:

After completing his university studies, Ernst Wehlage started in Darmstadt, Germany in the digital development of professional video systems for the future HDTV technology. FPGA technologies were used in complex systems at an early stage in order to achieve high data rates, which were decisive for the development of new, innovative film and video systems in high-resolution real-time processing. With over 30 years of professional experience in training and the application of programmable logic, the fascination of these possibilities is unbroken, as continually innovative technological leaps give hardware and software developers ever better methods. He has been a trainer in the PLC2 team since 2001 for almost all subject areas of the PLC2 training courses, projects FPGA and MPSoC based systems on behalf of customers and advises developers on how to solve their development tasks.

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