The latest update to STING includes the support to verify all the recent changes to the RISC-V user and privilege specifications, which include the latest draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been added to enable testing of virtualization use-cases. The new version also enables the capability of on-target test generation in STING for the post-silicon testing needs of RISC-V along with a new self-contained mode of execution which enables the ability of generation and execution of standalone STING tests.
"Verifying the compliance and functional correctness is a critical step in the development of CPU and SoC designs." said Shajid Thiruvathodi, CTO of Valtrix. "As the RISC-V specification continues to evolve and support more features and extensions, it becomes very important to have mature and versatile verification tools which can scale according to the complexity of the implementation. STING meets this need and enables adopters of RISC-V to verify and debug their designs quickly, easily and more efficiently".
The latest version of STING will be available for demonstration at the upcoming 3rd RISCV Summit from December 8-10. Attendees can arrange meetings to discuss about STING and its support for RISC-V implementations by writing to firstname.lastname@example.org.
For more information on Valtrix's design verification technology and products, visit https://www.valtrix.in
About Valtrix's STING Design Verification Tool
STING, the flagship product of Valtrix, is a design verification platform for RISC-V based implementations. It can be configured to generate portable bare-metal programs containing selfchecking architecturally-correct test stimulus, which can then be enabled on simulation, FPGA prototypes, emulation or silicon. STING also provides a RISC-V architecture verification suite to provide users an easy ramp into verification readiness.
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SOURCE Valtrix Systems
|Company Name: Valtrix Systems