DVCon U.S. 2021 Provides Outstanding Technical Program on Virtual Platform

GAINESVILLE, Fla., Jan. 21, 2021 (GLOBE NEWSWIRE) -- The 2021 Design and Verification Conference and Exhibition ( DVCon) U.S. will be held on a virtual platform with a combination of recorded and live Q&A. The information-packed technical program runs four days and includes 42 papers, four tutorials, 14 posters, two panels, 18 short workshops and a keynote focused on computational logistics for system and software verification. Sponsored by Accellera Systems Initiative, DVCon U.S will be held March 1-4, 2021.

“Our technical program committee has worked very hard to put together an informative, highly technical program that I think attendees will find very valuable,” stated Vanessa Cooper, DVCon U.S. 2021 Technical Program Chair. “Holding the 33rd annual DVCon on a virtual platform gives us the opportunity to reach an even broader audience of design and verification engineers with topics such as UVM and RISC-V, functional safety, portable stimulus, machine learning, SystemC, low power design, formal verification to name just a few. I think our audience will benefit a great deal with the opportunity to experience even more of the program with the on-demand elements provided by a virtual platform.”

The program is now available online and an early registration rate is available through January 31. Registration for the keynote, panels and exhibits-only is free.

In addition to the 42 technical papers, program highlights include:

Monday, March 1

  • A tutorial, “ Portable Stimulus 2.0 is Here: What You Need to Know” presented by members of Accellera’s Portable Stimulus Working Group.
  • 12 short workshops on Monday, including five presented by Accellera working groups and seven by sponsoring companies. Topics include functional safety, IP security, system-level power analysis, UVM-AMS, etc.

Tuesday, March 2

  • This year’s keynote, “ Computational Logistics for System and Software Verification,” on Tuesday, March 2 from 1:00pm-2:15pm will be given by Dr. Paul Cunningham, corporate vice president and general manager of the system verification group at Cadence Design Systems, Inc. In his presentation, Dr. Cunningham will introduce the concept of verification throughput and highlight the significant opportunities we have as an industry to dramatically improve verification throughput on modern SoC designs.
  • 14 Posters will be presented from 10:30am-noon

Wednesday, March 3

Thursday, March 4

  • Six sponsored short workshops on topics such as RISC-V based SoC design, verification and debug; functional debug; accelerating sign-off; verification coverage from safety to certification; Cloud as a platform enabling faster verification; hardware-software co-design & co-verification using ESL methodologies

The interactive Expo will be open Tuesday from 2:00pm to 5:00pm, Wednesday from 2:00pm to 6:00pm and Thursday from 12:30pm to 1:30pm. During the Expo there will be networking opportunities to give attendees the ability to meet online with peers and experts in the design and verification community.

For the complete DVCon U.S. 2021 schedule, including the full list of tutorials, short workshops, panels, posters, and virtual events, visit the program agenda.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

For more information, please contact:

Laura LeBlanc
Conference Catalysts, LLC
352-872-5544 Ext. 115
Email Contact
Barbara Benjamin
HighPointe Communications
503-209-2323
Email Contact


Primary Logo




Review Article Be the first to review this article

Featured Video
Editorial
More Editorial  
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Remembering Jim Hogan
Colin WallsEmbedded Software
by Colin Walls
Variable declarations in C – plenty of pitfalls
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
AUGER: Celebrating Our Users
Jobs
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Upcoming Events
IPC APEX EXPO 2021 Goes Virtual at - Mar 8 - 12, 2021
ADAS Sensors 2021 at The Henry Hotel 300 Town Center Drive Dearborn MI - Apr 7 - 8, 2021
ISQED'21 - 22nd International Symposium at POB 607 Los Altos CA - Apr 7 - 9, 2021
SEMI MEMS & Sensors Industry Group (MSIG), MSTC 2021 at United States - Apr 13 - 15, 2021
Verific: SystemVerilog & VHDL Parsers



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise