Palladium Z2 and Protium X2 Cadence

Michael Munsey & Brad Hart Perforce

Aparna Dey, U.S. General Chair DVCon

EDACafe Editorial by Roberto Frazzoli Nvidia’s datacenter CPU; fast AI training on x86; Siemens acquires OneSpin; EDA Q4 results

IC Insights by IC Insights Chinese Companies Hold Only 5% of Global IC Marketshare

Bridging the Frontier by Bob Smith, Executive Director What’s on Tap from the ESD Alliance? Plenty! Read On …

Aldec Design and Verification by Farhad Fallahlalehzari How does the Mars Perseverance rover benefit from FPGAs as the main processing units?

Agnisys Automation Review by Anupam Bakshi Automating IP and SoC Development

Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California

Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California

SoC Physical Design Engineer for Qualcomm at Austin, Texas

Business Operations Planner for Global Foundaries at Santa Clara, California

Test and Measurement System Architect for Xilinx at San Jose, California

SerDes Applications Design Engineer for Xilinx at San Jose, California

Virtual ASMC 2021 at United States - May 10 - 12, 2021

DVCon China 2021 at Shanghai China - May 26, 2021

CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021

DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021