Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer

As a top industry executive, holding prior roles at Qualcomm and NVIDIA, Moll brings strategic leadership as the company drives system-on-chip IP integration growth.

CAMPBELL, Calif., April 14, 2021 — (PRNewswire) —

CAMPBELL, Calif., April 14, 2021 /PRNewswire-PRWeb/ -- Arteris IP, a leading provider of network-on-chip (NoC) interconnect and other intellectual property (IP) technology that manages the on-chip communications in system-on-chip (SoC) semiconductor devices, today announced it is proud to welcome Laurent Moll as Chief Operating Officer (COO). Laurent will be responsible for managing all aspects of engineering functions and operations at Arteris IP. He will participate in the company's growth strategies and oversee the successful delivery of its industry-leading semiconductor designs as Arteris IP increases in scope and market share.

Laurent Moll most recently served as Vice President of Engineering at Qualcomm. He led a 500-person team creating infrastructure IP for Qualcomm's chips, including NoC interconnects, memory subsystems, cache coherency subsystems and more. Laurent has led a storied career for over two decades, performing key technical roles at industry leaders such as Digital Equipment Corporation, Compaq Computer Corporation, SiByte, Broadcom, Montalvo Systems and NVIDIA. Prior to his nearly 8-year tenure at Qualcomm, he was the Chief Technology Officer at Arteris Inc, a predecessor company of Arteris IP. Throughout his career, he has played an influential role in inventing the system-on-chip architectures, IP subsystems, and methodologies that are today the foundation of modern semiconductor design. Laurent holds over 60 patents on various aspects of SoC technology.

"I am thrilled to be part of the Arteris IP executive team. My entire career has been spent inventing ways to increase the efficiency of system-on-chip development so that design teams of all sizes and expertise can create world-class chips, and I am excited to pursue that common vision with my Arteris IP colleagues," said Laurent Moll, chief operating officer of Arteris IP.
"We are excited to welcome Laurent back to our team at Arteris IP," said K. Charles Janac, President and CEO of Arteris IP. "Laurent will not only bring his expertise and experience to focus on our company's technology evolution but will also provide additional leadership to solidify our SoC integration IP position."

About Arteris IP
Arteris IP provides network-on-chip (NoC) interconnect IP and IP deployment technology to accelerate system-on-chip (SoC) semiconductor development and integration for a wide range of applications from AI to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Bosch, Baidu, Mobileye, Samsung, Toshiba and NXP. Arteris IP products include the Ncore® cache coherent and FlexNoC® non-coherent interconnect IP, the CodaCache® standalone last level cache, and optional Resilience Package (ISO 26262 functional safety), FlexNoC AI Package, and PIANO® automated timing closure capabilities. Customer results obtained by using Arteris IP products include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit or find us on LinkedIn at

Arteris, FlexNoC, Ncore, CodaCache, PIANO, Arteris IP and the Arteris IP logo are registered trademarks of Arteris, Inc. All other product or service names are the property of their respective owners.

Media Contact

Kurt Shuler, Arteris IP, 4084707300, Email Contact



Company Name: Arteris IP

Review Article Be the first to review this article

 Advanced Asembly

Featured Video
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
IBM’s 2nm chip; EDA updates; AI updates; acquisitions
More Editorial  
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Next Week’s Main Event: The ESD Alliance CEO Outlook
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating the UVM Register Abstraction Layer (RAL)
Business Operations Planner for Global Foundaries at Santa Clara, California
SoC Physical Design Engineer for Qualcomm at Austin, Texas
Test and Measurement System Architect for Xilinx at San Jose, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Sr Engineer - RF/mmWave IC Design for Global Foundaries at Santa Clara, California
Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California
Upcoming Events
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
Verific: SystemVerilog & VHDL Parsers

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise