Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments

HSINCHU CITY, TAIWAN, April 23, 2021 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the new upgrade of AndeSight™ IDE v5.0, which targets to accelerate RISC-V AI and IoT developments by strengthening several innovative and useful features.

AI and IoT applications are blooming everywhere. The products serving the market must not only come with good performance, high efficiency, and low power consumption to meet the constraints for computing and energy, but also need to reduce time-to-market to respond to the ever-changing market needs. AndeSight™  IDE v5.0 rolls out new functions to address those issues, and brings the ultimate runtime performance and development efficiency to users.

The core for AI computations: RISC-V DSP/SIMD extension (RVP), vector extensions (RVV), and the tools and runtime from AndeSight™ IDE

RVP exactly addresses the balance between low-volume data computation and power consumption. By providing the compact SIMD (Single Instruction Multiple Data) and DSP (Digital signal processing) capability, it forms a very competitive basis for the TinyML, AIoT, and signal processing applications on edge and endpoints. RVV targets high-volume data computation, no matter in the edge or cloud, it provides very scalable, efficient, and powerful compute capabilities for general AI, NN, and data processing applications.

To unlock the potential of a powerful ISA extension, a simple and straightforward programming model is critical. AndeSight™ IDE v5.0 supports toolchains for the standard-bound specification of RVP and RVV, highly-optimized DSP and Vector libraries, intrinsic functions, and sample codes to guide code optimization. A key advantage is that software developers can build applications completely in C using efficient intrinsic and optimized libraries APIs, freeing developers from writing error-prone assembly code, and matching the performance of the same applications built with hand-code assembly.

To explore the full capabilities of processors and achieve the ultimate performance, an advanced processor pipeline analyzer is needed. AndesClarity™ visualizes the performance and resource bottleneck. Stall bubbles and data dependency are shown clearly along with the instructions, the C source code, and hardware functional units.

In addition, Andes provides the “Andes NN Library” that dramatically speeds up the development of Neural Network algorithms. It achieves a 66x speedup of MobileNet-v1 with half-precision floating-point, 256-bit SIMD width, and 512-bit vector length over RISC-V baseline extension. Moreover, “TensorFlow Lite for Microcontroller” can execute all built-in NN models with Andes NN Library on development boards.

Develop up-to-date RTOS and Linux applications along with AndeSight™ IDE powerful tools

AndeSight™ IDE v5.0 supports Linux LTS (Long-Term Support) kernel v5.4, and the popular RTOS such as FreeRTOS and Zephyr. Andes Linux kernel has verified with LTP (Linux Test Project), and seamlessly booted with Fedora or Debian Linux distro on Andes development boards along with the device drivers. To provide a smaller image for embedded Linux applications, Andes also offers RISC-V 32-bit Linux kernel to run on the corresponding Andes processors. Andes FreeRTOS port has passed the “AWS Qualification Program for RTOS”, which validates the pre-integrated port on  microcontroller-based boards by AWS (Amazon Web Service)1. Andes Zephyr port supports SMP (Symmetric Multi-Processing) and has been verified on Andes RISC-V multicore. Developers only need to focus on the application itself and do not need to worry about the fundamental software.

To further enhance the ultimate debugging efficiency, the versatile features of scripting and grouping are enabled by AndeSight™ IDE. AndeSight™ scripting can record the UI operations from one developer, and replay on another environment. It saves time to reproduce issues from the field. Similar to GDB Python scripts feature, users can automate and scale the debugging procedures with Python programming. “Core Grouping” is a useful feature to allow users to develop the multicore software with separate build and debug configurations, and sending debug commands to a specific set of cores at the same time.

AndeSight™ IDE v5.0 comprehensive features enriched from 16-year continuous development, including but not limited to the outstanding toolchains, highly-optimized C libraries, AndeSim™ near cycle simulator, easy-to-use profiling and analyzing tools, virtual hosting, RTOS awareness, and abundant reference codes.

“We are excited to announce that AndeSight™ IDE v5.0 is ready for release. AndeSight™ IDE v5.0 is the new milestone of our RISC-V software solutions. It is the latest Andes offering for RISC-V community, and we expect it to speed up RISC-V SoC development to a new level.” said Andes President and CTO Dr. Charlie Su. “Comprehensively optimized tools and runtime are the other sides of a coin. Processors cannot work efficiently and perform outstandingly without matching software solutions. We’ll continue to invest in our RISC-V software solutions to bring the best performance for RISC-V processor solutions to the RISC-V community.”

AndeSight™ IDE v5.0 will be available for licensing after June 2021. For more details of the AndeSight™ features, please visit Andes Webinar ( http://www.andestech.com/en/webinar_en/) and register the talk “Accelerating RISC-V AI and IoT Development with Andes Software Solutions” at 10:00 AM (CEST) and 09:00 AM (PDT) in Arp 28 (Thu.).

1: https://devices.amazonaws.com/detail/a3G0h0000077Y9QEAU/Corvette-F1-N25

About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions and a major player in pushing RISC-V into the mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as its base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue, and/or multi-core capabilities. Visit Andes at  https://www.andestech.com


Hsiao-Ling Lin 
hllin@andestech.com

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