Live Webinar: VHDL-2019: Just the New Stuff Part 4: Testbench Enhancements

Aldec
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Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 24th, 2021

Abstract:

Abstract: 

In this fourth webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's Testbench coding capabilities.

Many do not think of VHDL as a verification language, however, with the updates in VHDL-2002, 2008, and now in 2019, VHDL has increased its programming capability and is quite adept at creating good testbenches. Add to that methodologies and libraries such as Open Source VHDL Verification Methodology (OSVVM), and VHDL has become competitive with SystemVerilog+UVM.  

We have already covered some important items relevant to advanced VHDL testbench capability, such as Interfaces (Part 1), conditional analysis (Part 1), File IO (Part 1), and Protected Types (Part 2).   

This presentation furthers the discussion of Testbench enhancements and covers the following:

  • Composites of File Types
  • Functions with Access Type Parameters
  • Functions with Out and InOut Parameters
  • API for Assert
  • Relax library requirements on configurations
  • Map subprogram generics on call
  • Report calling path of subprograms
  • Garbage collection

About VHDL-2019

VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulation and synthesis) community that the users want these features.

Through its revisions, 1987, 1993, 2002, 2008, and now 2019, VHDL has evolved to be capable design and verification language.   

Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.

What about Verilog and SystemVerilog? Despite overwhelming marketing for SystemVerilog, it is clear from the Wilson Verification Survey, that VHDL is the preferred FPGA design and verification language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.  

The VHDL standards committee work is never done. It takes a collaboration of people with different skills to successfully update the standard. Some of these members are language experts, some design experts, and some verification experts. Join us in writing the next revision. See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome .

Agenda:

  • 50 min presentation/live demo
  • 10 min Q&A
Event Info
EU Session
3:00 PM – 4:00 PM CEST
 Thursday, June 24th, 2021
Register for EU Session
US Session
 11:00 AM – 12:00 PM PT
Thursday, June 24th, 2021
Register for US Session
Presenter  

Jim
                                                                                                                    Lewis

Bio:

The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.  

Whether teaching, developing OSVVM, doing consulting VHDL development, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.

 

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