December 1, 2021 - Laguna Hills, CA - Excellicon Inc. an innovative provider of comprehensive end-to-end timing constraints and clock solutions further expands its portfolio by offering new shift-left capabilities by enabling RTL development and integration teams to explore, define, and verify their physical implementation scenarios prior to hand off to physical implementation stages.
Initial phases of the chip design involves huge amount of planning where designers try to estimate the area, data flow, clock topology etc., in order to determine the ideal partitioning candidates for hardening which is needed for optimal floorplan that meets the PPA targets. This is followed by a preliminary floorplan which is refined multiple times as more accurate information becomes available as the chip undergoes the rest of the implementation process.
However, RTL development, partitioning decisions and floorplanning is often done independent of each other, which often leads to highly suboptimal results. Consequently, multiple expensive iterations are needed in order to meet the target PPA.
ConStruct streamlines the whole process by enabling the RTL or Implementation engineers, early access to all the information needed to rapidly derive (manually or automatically) optimal partitions and the floorplan. This is achieved by performing RTL analysis, exploring the area, timing, connectivity, data-flow and other factors. Using Excellicon’s ConStruct designers are now able to generate multiple floorplan scenarios so they can explore and choose the optimal solution.
ConStruct also provides the capability to validate the existing floorplan against the RTL (as well as other factors) so that the floorplanning or RTL issues can be identified at an early stage. RTL design without considering the physical ramifications and vice-versa, generally lead to expensive iterations where either the RTL or the floorplan needs to be modified. ConStruct is the only tool in the industry that adds the floorplan verification at an early stage. Exhaustive set of rules check for inconsistencies between the RTL, Floorplan, Port placement and Routing etc.
“We recognize that the RTL design without physical design consideration will result in a very time consuming and costly loop of iterations between front and backend teams, where either one or both teams have to make changes to design and layout” said Himanshu Bhatnagar CEO of Excellicon. “ConStruct is the only tool in the industry which enables exploration of RTL for partitioning, floorplanning and for floorplan verification at very early stages of design”, he continued.
Excellicon is an innovative provider of comprehensive end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products, ConMan, ConCert, ConCert-ET (Exceptions Toolbox), and ConCert-BT (Budgeting ToolBox), ConCert-Equivalence Checker, ConTree (CTS Guidance), ConStruct (Partitioning/Floorplanning), address the needs of designers at every stage of SOC design and timing closure and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
For further information contact: