TimeCraft's New Built-in Advanced On-Chip-Variation Analysis Improves Accuracy and Productivity for 90nm and 65nm Timing Sign-off
TimeCraft's advanced OCV engine provides both level- and location-based OCV analysis to address the effects of on-chip statistical process variation, which can no longer be ignored in nanometer designs. It effectively eliminates excessive guard banding, improving timing accuracy and reducing the effort to close timing closure. The native engine-based implementation approach is easy to use without limitation and delivers the best performance in runtime and memory usage when compared to other available solutions.
"With our new advanced OCV capability, TimeCraft continues to establishes itself as the leader in nanometer timing analysis and signoff," said Arthur Wei, Vice President of Operations at Incentia. "Its introduction continues our commitment to offer the best-of-the-class timing tools."
What's New: Advanced OCV
Traditional OCV uses a constant derating factor and may impose unnecessary performance penalties on nanometer designs. These penalties include reduced performance, larger die sizes and longer design cycles. TimeCraft's advanced OCV uses variable derating factors based on logic level and physical location to select the optimal derating factor for each timing path. This results in fewer timing violations, and allows design teams to rapidly achieve timing closure. It also provides an effective alternative to the difficult problem of using statistical analysis to model process variations. Furthermore, the OCV engine is integrated with TimeCraft to deliver the best analysis performance in runtime and memory usage. This improves turnaround time and reduces design cycles.
Price and Availability
TimeCraft with Advanced OCV is available now for Sun Solaris (32-bit and 64-bit), Linux (32-bit and AMD 64-bit), and HP (32-bit and 64-bit) platforms. For pricing and availability information, please contact Incentia.
About Incentia Products
Incentia Design Systems, Inc. offers advanced complete timing and synthesis solutions to address the ever-growing design challenges in performance, runtime, and capacity for multi-million-gate, nanometer SoC designs.
TimeCraft is fast a full-chip, gate-level static timing analyzer (STA). TimeCraft provides the capability to accurately analyze and close timing on complex SoC designs. Its rich features enable timing verifications at the pre-signoff (ECO iteration) stage and final signoff for all kinds of design applications.
DesignCraft is a complete logic synthesis tool with integrated capabilities for optimizing area, power, timing and design-for-testability (DFT). It produces aggressive area reduction and low power results, with advantages in runtime and capacity.
Incentia Design Systems, Inc. is a leading provider of advanced timing and synthesis software that addresses the stringent requirements of runtime, design capacity, timing, area, design-for-testability, power consumption and signal integrity for multi-million-gate semiconductor designs. The company's products are in use at leading fabless IC design, systems, semiconductor and design service companies and have successfully been used to tape out numerous designs in different design applications, such as communications, networking, wireless, chipset, consumer electronics, and multi-media.
Incentia has offices in Santa Clara, California and Hsinchu Science Park, Taiwan, as well as distributors in Japan, China, Korea, India and Israel. For more information, please visit www.incentia.com, email Email Contact or call 408-727-8988.
Georgia Marszalek, ValleyPR for Incentia, +1 650 345 7477, Email Contact
All other trademarks and tradenames are the property of their respective holders.