STARC Adding Sequence Power-Gating Analysis to Advanced Design Flow

SANTA CLARA, Calif.—(BUSINESS WIRE)—June 4, 2007— Sequence Design, the EDA leader in power-aware SoC design solutions, today announced its CoolTime-PGA (Power Gating Analysis) will be added to the Japanese Semiconductor Technology Academic Research Center (STARC) advanced design flow, STARCAD-CEL.

STARCAD-CEL addresses the challenges of very advanced process technologies including 65nm, 45nm and 32nm. The STARCAD-CEL design methodology is shared amongst the top Japanese semiconductor companies that comprise STARC's membership as a standard digital design platform.

According to Nobuyuki Nishiguchi, vice president and general manager, Development Department-1 at STARC, CoolTime-PGA's rush current and wakeup time analysis for MTCMOS designs achieved near-perfect correlation with SPICE simulations in a mere fraction of the time. "CoolTime-PGA is a fast, accurate analysis engine that will be a fine complement to other outstanding technologies in the STARCAD-CEL flow."

CoolTime offers a fast "what-if" PGA capability that enables users to rapidly determine switch turn-on sequence to control peak rush current and minimize wake-up time. Rush current analysis examines the peak current required by a gated block as it turns on, and calculates the impact of this current on the power grid to other active sections of the chip. Wake-up time analysis determines how long it takes for instances in the power-gated block to reach the nominal supply voltage and be function and timing ready. CoolTime's PGA capability provides "what-if" rush current and wake-up time analysis results within an hour instead of the days consumed by conventional methods.

STARC is a research consortium of major Japanese semiconductor companies developing leading-edge system-on-chip (SoC) design methodologies. For more information: www.starc.jp/index-e.html

About Sequence

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets. For more information: sequencedesign.com.

All trademarks mentioned herein are the property of their respective owners.

Contact:

Sequence Public Relations
Jim Lochmiller, 541-821-3438
Email Contact




Review Article Be the first to review this article
 Advanced Asembly

Featured Video
Editorial
More Editorial  
Latest Blog Posts
Colin WallsEmbedded Software
by Colin Walls
Variable declarations in C – plenty of pitfalls
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
AUGER: Celebrating Our Users
2021 EDACafe PredictionsEDACafe Editorial
by 2021 EDACafe Predictions
Atmosic Technologies Electronics Design Industry Predictions
Jobs
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Business Operations Planner for Global Foundaries at Santa Clara, California
ASIC Engineer for Amazon at seattle, Washington
Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California
Upcoming Events
DVCon U.S. 2021 at Virtual - Mar 1 - 4, 2021
IPC APEX EXPO 2021 Goes Virtual at - Mar 8 - 12, 2021
ISQED'21 - 22nd International Symposium at POB 607 Los Altos CA - Apr 7 - 9, 2021
ADAS Sensors 2021 at The Henry Hotel 300 Town Center Drive Dearborn MI - Apr 7 - 8, 2021
Verific: SystemVerilog & VHDL Parsers



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise