LatticeSC/M FPGA devices, with their industry-exclusive SONET flexiPCS block, enable telecom equipment vendors to implement programmable SONET/SDH solutions at a lower cost, lower power and faster time to market. Additional embedded IP is also available on the MACO-enabled LatticeSCM devices to build high performance Packet over SONET (PoS) bridges and gaskets.
Delivering a timing solution that is both jitter compliant and frequency flexible, the Silicon Labs' multi-rate CDR, XOs and clock products can be used in conjunction with the LatticeSC FPGA for a complete SONET solution. The Si5023 multi-rate CDR is able to minimize data jitter associated with the LatticeSC device's SERDES outputs while Silicon Laboratories' crystal oscillator and clock devices provide easily reprogrammable reference clock frequencies to the FPGA.
"Silicon Laboratories is committed to providing customers with easy-to-use timing solutions for the telecommunication market," said David Bresemann, vice president of Silicon Laboratories. "By joining Silicon Labs' innovative timing solutions with a Lattice FPGA, we are ensuring a seamless solution for a challenging design problem for our customers."
"Our LatticeSC/M FPGA devices are the ideal programmable platforms for Packet over SONET, Multi-Service or DWDM FEC line-cards. We are very pleased to announce our cooperation with Silicon Laboratories to provide our mutual customers with programmable TDM solutions that meet the strict performance and jitter criteria for SONET/SDH compliance," said Stan Kopec, Lattice corporate vice president of marketing.
About Silicon Laboratories' Si5023, Si570 and Si5326
The Si5023 Multi-rate CDR attenuates high frequency jitter while performing clock and data recovery from a serial input at OC-48/12/3, STM-16/4/1, Gigabit Ethernet (GbE) and 2.7Gbps forward error correction (FEC) rates. The device does not require an external reference clock for lock acquisition. By leveraging Silicon Labs' proprietary DSPLL® technology, the external loop filter components necessary in traditional CDR implementation are eliminated, reducing device sensitivity to board-level noise and improving jitter performance.
The Si570 device is the industry's first user-programmable XO packaged in an industry standard, RoHS-compliant 5- x 7-mm surface mount package with two extra pins for I2C frequency programmability. The device supports orderable options for temperature stability, APR and output signal format. The Si5326 device is an Any-Rate clock packaged in a 6- x 6-mm QFN with I2C/SPI interface for input/output frequency and PLL bandwidth programmability. This device is typically used for generating a clean reference clock for transmitting SONET data. Both the Si570 and Si5326 support output frequencies up to 1.4 GHz with ultra-low jitter performance (< 0.3 ps-rms typical from 50 kHz to 20 MHz) suitable for 10 Gbps applications.
About the LatticeSC/M FPGA Family
The Extreme Performance LatticeSC family is designed to provide the unsurpassed performance and connectivity essential for high-speed applications. Fabricated on Fujitsu's 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity. The LatticeSC family offers LUT counts up to 115K LUTs and 32 SERDES channels.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbps data rates, PURESPEED parallel I/O providing industry-leading 2Gbps speed, innovative clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM (up to 7.5 megabits of block RAM in a single device). Lattice's unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as SPI4.2, Ethernet MAC and PCI Express control functions developed by Lattice to shorten end-system time to market.
About Silicon Laboratories
Silicon Laboratories is an industry leader in the innovation of high-performance, analog-intensive, mixed-signal ICs. Developed by a world-class engineering team with unsurpassed expertise in mixed-signal design, Silicon Labs' diverse portfolio of highly integrated, easy-to-use products offers customers significant advantages in performance, size and power consumption. These patented solutions serve a broad set of markets and applications including consumer, communications, computing, industrial and automotive. For more information about Silicon Laboratories, please visit www.silabs.com.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party silicon suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeSC, LatticeSCM, Extreme Performance, flexiPCS, PURESPEED, MACO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
EDITORIAL/READER CONTACT: Brian Kiernan Corporate Communications Manager Lattice Semiconductor Corporation 503-268-8739 voice 503-268-8193 fax Email Contact