Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips

SAN JOSE, CA -- (MARKET WIRE) -- Nov 12, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today introduced Cadence® Virtuoso® Passive Component Designer, a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. The new technology puts passive component design into the hands of analog and RF designers developing fast and complex wireless SoCs and RFICs. Starting from design specifications such as inductance, quality factor and frequency, the Virtuoso Passive Component Designer helps designers automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area. A built-in accurate 3D full wave solver verifies the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turnaround time.

Virtuoso Passive Component Designer is optimized for 90- and 65-nanometer process nodes, supporting advanced design rules and CMP constraints such as dummy metal fills and slotting. In addition to the wide variety of supported inductor and transformer geometries, it allows the design teams to define their own custom geometries graphically or manually using parameterized cells, or Pcells.

"Inductors and transformers are critical components in our high frequency integrated circuit. They have high impact on chip area and performance," said Hisaharu Miwa, general manager of the Design Technology Division, Renesas Technology Corp. "Our goal is to improve design productivity by considering the impact of inductors and transformers from the early design stages. We use Virtuoso Passive Component Designer because it addresses these challenges. Virtuoso Passive Component Designer provides an easy way to model and generate PDK components due to its integration in Virtuoso custom design platform and its accurate built-in electromagnetic solver."

Virtuoso Passive Component Designer is easy to use and does not require electromagnetic expertise. The output is a complete process design kit component with a symbol, schematic, layout and a simulation model. The built-in modeling capability converts S-parameter files into physical lumped element models, ready for RF analysis using Virtuoso Spectre® Circuit Simulator XL. The new Cadence technology also includes a fast and accurate coupling analysis capability enabling designers to optimize the placement of inductors and transformers on the layout resulting in smaller silicon area and higher yield.

"We immediately improved the frequency accuracy of our VCO designs to 0.9 to 1.9% once we adopted the Cadence RF Design Methodology Kit and began to use Virtuoso Passive Component Designer to accurately synthesize and model our inductors and transformers," said Dr. Aleksander Dec, vice president and co-founder, Epoch Microelectronics, Inc. "The combination of detailed inductor models from Virtuoso Passive Component Designer and accurate RLCK extracted views from QRC extraction enabled accurate full-chip sign-off. This represented a huge savings in both time and cost."

Virtuoso Passive Component Designer is tightly integrated into the Cadence Virtuoso custom design platform. The new technology is a component of Virtuoso Multi-Mode Simulation technology and follows the same flexible licensing scheme.

"The evolution of cellular phones and portable devices presents great challenges for analog and RF IC designers," said Srinivas Raman, corporate vice president, Virtuoso Custom IC R&D. "More and more complex analog and RF circuits need to fit in the same small lightweight handset, consume the same amount of battery power, and be produced with the same low cost of a single-band handset of the 1990s. Using the Virtuoso Passive Component Designer, analog and RF design teams can quickly create accurate passive components that meet design specifications, consume lower power and fit in smaller areas than pre-designed one-size-fits-all components."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, Virtuoso and Spectre are registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
Direct: 408.944.7226

Email Contact

Review Article
  • October 09, 2008
    Reviewed by 'RFIsee'
    This press release reads as a new product announcement, but in effect Cadence VPCD is a
    a respin of VPCM, a product based on technology they acquired from Celestry that has been
    shipping bundled in MMSIM (simulators package) for some time now. As a matter of fact,
    I recognize one of the customer quotes from here:
    Other products compete for the same slot, such as Lorentz Solutions' Peakview and Helic's
    VeloceRF, both of which introduced support for 90- and 65-nm process nodes long ago.
    Lorentz offers a versatile API for developing custom spiral inductor PCells, while Helic's
    is the only solution that provides mutual inductance extraction (spiral to spiral, also supporting
    interconnect RLCK) without resorting to time-consuming EM analysis.
    Both tools boast customer wins with Tier 1 IDM and fabless companies.
    Cadence have reportedly spent considerable effort in bringing VPCM (now VPCD) to shape, but they
    need to get the use model right. Foundries and designers still have to spend significant time and
    resources to construct a PCell library which is 100% DRC and DFM-clean in 90/65nm CMOS. Also,
    accurately simulating single inductors and transformers is only part of the problem; extraction
    of complex layouts with multiple inductors and interconnects becomes necessary. For instance, how
    about VPCD-AssuraRF linkages?

      Was this review helpful to you?   (Report this review as inappropriate)

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