First-Time-Ever Full-Circuit Performance Simulation of PLL Synthesizer For Wideband Satellite TV Tuner with True SPICE Accuracy
Santa Clara, CA — March 25, 2008— Berkeley Design Automation Inc., provider of Precision Circuit Analysis technology for advanced analog and RF integrated circuits (ICs), today announced that the company's Analog FastSPICE circuit simulator has delivered an industry first full-circuit PLL synthesizer performance simulation with true SPICE accuracy. The application is a wideband RFCMOS satellite TV tuner under development at the Berkeley Wireless Research Center at the University of California Berkeley.
"We are doing pioneering work in the integration of the complete RF front-end of a wideband satellite TV receiver (LNA, mixer, frequency synthesizer) in CMOS technology. This integrated RFCMOS approach will dramatically reduce the costs for such receivers while enabling multi-standard, multi-network operation," said Ali Niknejad, Associate Professor of Electrical Engineering and Computer Sciences at UC Berkeley, and co-director of the Berkeley Wireless Research Center. "With Analog FastSPICE, we were able to verify the complete 10GHz full-circuit PLL synthesizer for this wideband satellite TV tuner at the transistor-level with true SPICE accuracy which was impossible with any other simulator."
Berkeley Design Automation tools include Analog FastSPICE circuit simulation, RF FastSPICE periodic analyzer, and PLL Noise Analyzer. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.
Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems. Typical applications include characterizing complex blocks (e.g., PLLs, ADCs, DC:DC converters, PHYs, Tx/Rx chains) and running performance simulation of full circuits (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).
"We are very pleased with our cooperation with the Berkeley Wireless Research Center," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "The center's on-going research on highly-integrated wideband RFCMOS solutions with the lowest possible energy consumption and advanced circuit architecture innovations pushes verification tools to the limit. We are very proud that our Precision Circuit Analysis technology is an essential component of their success in developing breakthrough RFCMOS architectures for next-generation wireless systems."
About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine’s 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see
About Berkeley Wireless Research Center
The Berkeley Wireless Research Center is a pioneer in a new wave of university-industry-government partnerships. The Center is focused on forging deep relationships with leading wireless companies so that industry can rapidly transfer new technologies and university researchers can benefit from industrial experience. BWRC provides an environment for research into the design issues necessary to support next generation wireless communication systems and expand the graduate research program in the wireless segment. For more information, see