eASIC Issues $30,000 Worldwide Placement Design Challenge - Everyone Welcome to Participate

SANTA CLARA, Calif.—(BUSINESS WIRE)—April 28, 2008— eASIC Corporation, a provider of zero-mask charge ASIC devices, today announced a $30,000 placement design challenge. This challenge is designed to inspire innovation in the area of placement algorithms. eASIC will offer a total prize of $30,000 to the individuals or groups that can implement the most efficient placement algorithms.


Eligible design challenge contestants can submit proposals either as teams or as individuals. To facilitate this design challenge, eASIC will provide design examples, utilities for evaluation, and representations of its unique architecture.

We have completed many designs to date and believe that the design tools and methodologies used exploit the uniqueness of our silicon, said Dr. Herman Schmit, Vice President of Technology at eASIC Corporation. But when you are in the business of disruption and innovation, one must keep an open mind and strive to avoid the pitfall of incremental improvements as we have seen with FPGA design tools. The design challenge will hopefully excite the open community and will foster radical new ideas and methodologies.

Dr. Schmit continued, This design challenge reflects eASICs commitment to building an innovative software organization--one that combines collaborative world-wide research and the open source community. Just like our silicon technology, which is enabling everyone to get their ideas to production silicon, the design of our future software will enable innovative EDA engineers to participate in the creation of a uniquely powerful software system.


Individuals and groups are invited to participate in eASICs Placement Design Challenge. Registration is now open and design challenge rules will be available for registered parties starting from May 1, 2008. To register, please visit: http://www.opensourceeda.org

About eASIC

eASIC is a fabless semiconductor company offering breakthrough zero mask-charge ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer ASICs with no mask-charges and no minimum order quantity,

Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com.


Spencer Horowitz, 408-832-9616
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