FiPoP technology addresses the industry demand for a smaller, thinner stacked solution with increased device integration for advanced mobile phone and handheld applications. In conventional Package-on-Package (PoP) designs, the top package must be the same size as the bottom package in order to interconnect the top package to the bottom package during the board level reflow process. With consumer demand for increased performance in thinner and smaller portable handheld devices, the conventional PoP approach presents physical limitations in the reduction of the overall package size and height while maintaining acceptable surface mount yields and reliability levels.
FiPoP allows multiple logic, analog and memory die to be integrated in the bottom PoP package and accommodates larger die sizes in a reduced footprint as compared to conventional PoP designs. The key to the FiPoP design is an exposed array of land pads on the top center surface of the package, instead of a peripheral array around the top of the bottom package substrate as found in a conventional PoP. This eliminates the requirement of the top and bottom packages to be the same size, resulting in greater flexibility in stacking thinner, smaller memory packages on top. In addition, the FiPoP structure reduces package warpage and related board mount issues, as well as enabling finer ball pitch interconnect between the top and bottom package (down to 0.4mm pitch) and high package-to-package interconnect pincount.
"STATS ChipPAC has internally qualified both top and bottom packages in various body sizes. This qualification opens the door for a multitude of package configurations and provides semiconductor companies a flexible solution to meet their integration and miniaturization demands much sooner and at a lower overall cost," said Dr. Han Byung Joon, STATS ChipPAC's Executive Vice President and Chief Technology Officer.
The inherent design of FiPoP provides a more balanced structure that achieves high final assembly yields, meets rigorous package level reliability requirements and performs well above JEDEC board level reliability requirements for mobile phone and handheld applications.
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; level of competition; demand for end-use applications products such as communications equipment and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; availability of financing; prevailing market conditions; our ability to meet the applicable requirements for the termination of registration under the Exchange Act; our ability to meet specific conditions imposed for the continued listing or delisting of our ordinary shares on the SGX-ST; our substantial level of indebtedness; potential impairment charges; delays in acquiring or installing new equipment; adverse tax and other financial consequences if the South Korean taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop and protect our intellectual property; rescheduling or canceling of customer orders; changes in our product mix; intellectual property rights disputes and litigation; our capacity utilization; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; changes in customer order patterns; shortages in supply of key components; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labor union problems in South Korea; uncertainties of conducting business in China and other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks described from time to time in the Company's SEC filings, including its annual report on Form 20-F dated March 7, 2008. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP) is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the Singapore Exchange Securities Trading Limited (SGX-ST). Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
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