New Virtex-5 FPGA-based reference design delivers high performance, lower power programmable platform for faster, lower cost development of 3GPP LTE radio subsystems
The Xilinx(R) 3GPP LTE design supports a fully featured programmable development platform using Xilinx Virtex(R)-5 FPGAs, the industry's most widely adopted high-performance FPGA family. The LTE DFE platform consists of highly optimized blocks for Digital Up Conversion (DUC), Digital Down Conversion (DDC) and Crest Factor Reduction (CFR) that together form a complete LTE radio subsystem. It is compatible with existing Digital Pre-Distortion (DPD) designs from Xilinx, enabling systems architects to rapidly develop and integrate all the digital system elements of a high performance, commercial LTE system, and in a significantly shorter period of time than is feasible with traditional application-specific standard part (ASSP) and application-specific integrated circuit (ASIC) design methods, of which there are none currently available supporting LTE systems.
"LTE is set to be the dominant wireless standard over the coming years, and developers need to ensure that they have products available for operator trials within a small window of opportunity, and this window is rapidly closing," said David Hawke, senior product manager of Radio and Wireless Interfaces for Xilinx. "Our DFE reference design makes it easier for designers to leverage the systems knowledge, support and optimization skills that Xilinx has developed, and apply it to their own 3GPP LTE product developments, saving significant engineering costs, lowering total system power consumption, and accelerating their delivery timescales."
High Performance, Flexible 3GPP LTE Platform
Today up to 60 percent of the overall capital expenditure of a base station is within the radio, which is also responsible for much of the operational expenditure incurred during the lifetime of the product. The Xilinx 3GPP LTE platform with the embedded high performance, low power digital signal processing capabilities of Virtex-5 FPGAs enables operators to achieve significant cost savings in the development and operation of LTE radio equipment.
The LTE DFE design is highly configurable and has been architected to support seven single and multi-carrier implementations, including: single carrier 5, 10, 15, and 20 MHz bandwidths; dual carrier 5 and 10 MHz bandwidths; and four carrier 5 MHz bandwidth. With optimized solutions provided for each configuration, designers can select an implementation based on their system requirements, without paying a penalty on design area and helping to reduce overall system cost and power. Using the industry-leading Xilinx System Generator for DSP tool suite, the design also can be easily customized to meet the needs of company-specific 3GPP-LTE radio applications.
Pricing & Availability
The 3GPP LTE reference design is delivered with a comprehensive application note and design files for Virtex-5 device architectures, test vectors and scripts that allow designers to quickly evaluate the design performance in The MathWorks MATLAB(R) environment. Instructions for integrating the reference design into the target system design are also included. The design files, application note and integration instructions can be downloaded free of charge by registered Xilinx customers at: http://www.xilinx.com/esp/wireless.htm#rf
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