Toshiba Makes Major Advances in NAND Flash Memory with 3-Bit-Per-Cell 32nm Generation and with 4-Bit-Per-Cell 43nm Technology

TOKYO—(BUSINESS WIRE)—February 10, 2009— Toshiba Corporation (TOKYO:6502) today announced breakthroughs in multi-bit-per-cell technology for NAND flash memories that will bring advances in chip densities and cost savings to next generation devices. In the 32 nanometer (nm) generation, Toshiba has realized a 3-bit-per-cell 32 gigabit (Gb) chip with the world-smallest die size, and smaller than a 2-bit-per-cell 16Gb chip fabricated with 43nm technology, which is currently in the market. The cutting-edge chip will be mass produced in the second half of CY2009. The company has also fabricated the world’s first 64Gb chip that applies 4-bit-per-cell technology at the 43 nm process generation.

Toshiba and its technology partner, SanDisk, unveiled these key technology advances today at the International Solid State Circuits Conference (ISSCC) now underway in San Francisco, California.

Manufacturers of NAND flash memories must respond to demand for higher density with lower costs. Toshiba and SanDisk have done so through the application of its innovative technologies.

The 3-bit-per-cell 32nm generation device uses optimized circuit design for the row decoder and extended column architecture, which significantly contributed to a 113mm2 chip, the smallest die size yet achieved in this generation. The 4-bit-per cell applies super multi-bit programming technologies, which realizes 64Gb without increase in chip size, while achieving a write speed performance of 7.8MB/s.

Toshiba and SanDisk have maintained their continuing leadership in the development and manufacturing of advanced NAND flash memory. Toshiba will promote further development in leading-edge process technologies to further widen the scope of application and to expand the NAND flash memory market.


Toshiba Corporation
Kaori Hiraki, +81-3-3457-2105
Corporate Communications Office

Review Article Be the first to review this article

New Customer Special

Featured Video
Sr. Principal FPGA for Northrop Grumman Mission Systems at Morrisville, North Carolina
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Principal Electronics Engineer Test-20004966 for Northrop Grumman Mission Systems at Falls Church,, Virginia
Principal Circuit Design Engineer for Rambus at Chapel Hill, North Carolina
Upcoming Events
Embedded Vision Summit 2020 at Santa Clara Convention Center Santa Clara CA - May 18 - 21, 2020
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise