Cadence® is a corporate member of OSCI and a longtime contributor to its organizational and technical leadership. OSCI TLM 2.0 is an important advancement providing a standard to improve interoperability of transaction-level models and the transaction performance of those models for architecture analysis, software development, performance analysis, and hardware verification.
"OSCI TLM 2.0 is a critical advancement in our methodology, enabling further investment in SystemC TLM methodology and tooling. Cadence provides one of the most comprehensive mixed-level functional verification solutions available," said Karl Auker, director of Strategic Alliances at ARC International.
Cadence SystemC simulation support is part of a fully integrated multi-language, multi-level functional verification solution which now includes TLM extensions. The arrival of TLM 2.0 codifies the intent of SystemC such that the Incisive® Enterprise Simulator infers the transactional interaction information and presents TLM-aware control, visibility, and debug capabilities -- providing layers of abstraction above the C++ baseline. This removes the need to manually instrument source code, and organizes transaction information, multiple processes, and synchronization actions such as events. This enables the users to intuitively debug all the interacting elements of their SystemC TLM 2.0 design, using control and debug operations at the abstraction level of transactions, as well as software breakpoints, stack variables, and method and thread data operations for data structures such as fifos and sockets.
"OSCI TLM 2.0 is of great significance for the industry where the customer's benefits are multiplied by the support of each additional commercial product," said Stan Krolikoski, group director of Standards and Interoperability at Cadence, and the company's representative on the OSCI board.
Long runtimes are a common challenge for system-level verification. New Save/Restart and Reset capabilities have patent-pending extensions for SystemC/C++, enabling teams to start regressions from a deep state starting point, such as after booting the Linux OS. Saving the entire state of a SystemC/C++ program includes proper handling of pointers, memory addresses, and simulation variables -- far beyond the state of a mixed-language simulation.
"Cadence SystemC simulation environment provides the high-performance, multi-language capabilities we need to verify our energy-efficient high-performance computing systems," said Bryce Denney, director of ASIC Verification at SiCortex, Inc.
"The new capabilities of Cadence system-level verification dramatically magnify the benefits of transaction-level modeling, helping shave weeks off the creation of interoperable TLM models," said Ran Avinun, group marketing director of Cadence. "We have had great customer support for our solution, and we are committed to maintaining our leadership role in helping drive OSCI standards to meet the needs of systems verification engineers."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact