"The new STARCAD-CEL V3.0 Reference Flow addresses critical design-for-manufacturing concerns for 65nm, 45 nanometers and advanced process technologies," said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 at STARC. "Cadence Encounter Digital Implementation System with Litho Physical Analyzer provided very accurate litho hotspot detection and correction and one hundred percent correction of the catastrophic or yield limiting defects in our test design, while also providing a faster turnaround time."
The Cadence Litho Physical Analyzer harnesses the strength of multi-CPU parallel processing capabilities, along with proprietary, foundational algorithms delivering linear performance scalability and faster turnaround time as reported by STARC. Along with multiple advances in technology process modeling and integration with the Cadence Virtuoso® Custom IC and Encounter Digital Implementation Platforms, Cadence provides a complete "correct-by-design" digital implementation solution for cell/block to full-chip.
"The semiconductor industry and ecosystem recognizes Cadence DFM technologies as essential to advanced design methodologies today," said Dr. Chi-Ping Hsu, senior vice president of digital implementation research and development at Cadence. "It's the difference between identifying potential DFM issues during the design phase and fixing them right there in the system, versus discovering yield limiting defects during the manufacturing process, when it is too late. We are proud to be working closely with STARC to prove the advantages of our DFM technology and digital implementation solution for their 45 nanometer reference design flow."
Semiconductor companies worldwide are now requiring DFM analysis during the design phase, and the majority of the top 20 semiconductor companies have now adopted Cadence's DFM solutions to meet their accuracy, performance and yield goals.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, the Cadence logo, Encounter and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dan Holden Cadence Design Systems, Inc. 408-944-7457 Email Contact