SynTest Unveils MultiCoreScan framework for ATPG Speed-Up

"Tool Suite for Parallel, Hierarchical ATPG Using MultiCore CPU Workstations"


SAN JOSE, Calif., July 21, 2009 - SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, is unveiling a MultiCoreScan framework for its Automatic Test Pattern Generation (ATPG), Logic Built-In Self-Test (BIST) and Fault Simulation (FSIM) product lines. The framework allows multifold performance enhancement of test generation and verification process.

Overall effectiveness of Scan ATPG patterns is measured in three distinct components: (1) Number of Patterns generated (affects test cost) to achieve, (2) Highest Fault Coverage (affects quality), and (3) time it takes to generate the patterns (affects design time). SynTest's patented technique ("At-Speed Staggered Launch-on-Capture [LOC] as well as Launch-on-Shift [LOS] for designs with multiple clock domains") for generating most compact ATPG patterns is unmatched in the industry. To achieve highest fault coverage, SynTest employs a hybrid capture scheme by augmenting the staggered capture patterns with "one-hot" capture patterns.

MultiCoreScan framework being announced at 2009 Design Automation Conference is aimed at minimizing the time it takes for pattern generation. Many more patterns are needed for testing for new causes of failures, such as small-delay defects and bridging faults, improving quality of first-silicon validation, and improving yield by carrying out volume diagnosis via diagnostic testing, measurements, and analysis for every fabricated chip. ATPG has extremely high storage and run-time complexities; it is no longer possible to simply depend on the next generation processors to ease performance bottlenecks. The MultiCoreScan framework employs commercially available "multicore processor architecture" to (1) accelerate the performance for each software module by running it on a single processor core, and (2) effectively utilize all available cores, without sacrificing the acceleration achieved on each individual processor.

"Long ATPG runtime has been a major limiting factor for generating quality patterns for detecting various types of manufacturing faults for multimillion-gate designs. With additional requirement of test compression coming into the picture, the runtime can grow linearly as gate size doubles. The newly developed multicore ATPG framework can now reduce ATPG runtime to 6.5 hours for a 10-million gate design on an AMD dual-core CPU," said L.-T. Wang, founder, president & CEO of SynTest.

"Customers seeking fast turnaround on ATPG performance can now count on newly announced MultiCoreScanTM framework from SynTest. With support provided by the most dedicated support team, coupled with attractive pricing on a site-license basis from SynTest, DFT engineer's dream ATPG tool set is here now," added Ravi Apte, SynTest Vice President of Marketing.

About SynTest
SynTest Technologies, Inc., established in 1990, develops IP for advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) applications (including logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, and silicon debug and diagnosis) and markets them throughout the world, to semiconductor companies, system houses and design service providers. SynTest products improve an electronic design's quality and reduce overall design and test costs. SynTest is headquartered in Sunnyvale, California, and has field offices in Taiwan, Japan, Korea and China, and distributors in Europe, Asia, and Israel. More information regarding SynTest is available at www.syntest.com.

SynTest Technologies Inc.
505 South Pastoria Ave., Suite 101
Sunnyvale, California 94086
Phone: 408-720-9956
E-Mail: Email Contact

Acronyms:
ATPG - Automatic Test Pattern Generation
BIST - Built-In Self-Test
DFD - Design-for-Debug/Diagnosis
DFT - Design-for-Test
FSIM - Fault Simulation
LOC - Launch-on-Capture
LOS - Launch-on-Shift
IC - Integrated Circuit

Press Contact:
Ravi Apte,
408-720-9956 x 300


© SynTest Technologies, Inc. 2008. All Rights Reserved. SynTest and TurboBIST-Logic are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.

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