Mentor Graphics Provides Comprehensive Low Power Solution in TSMC Reference Flow 10.0

WILSONVILLE, Ore. — (BUSINESS WIRE) — September 21, 2009 — Mentor Graphics Corporation (NASDAQ: MENT) today announced that its low power RTL-to-GDSII tool flow has been included in Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 10.0. TSMC and Mentor worked together nearly a year to validate and deliver a robust set of tools with proven support for the Unified Power Format (UPF).

“In addition to expanding the Mentor reference flow to add both functional verification and implementation technologies, Mentor is addressing new challenges such as low power,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

The Mentor low power track includes the 0-In® CDC, Questa®, FormalPro, Olympus-SoC and TestKompress® tools.

  • The 0-In CDC tool provides a three-fold verification approach for clock domain crossings, checking for appropriate synchronization through structural analysis, protocol verification, and accurate simulation of metastability effects.
  • The Questa platform enables early verification and evaluation of power architectures starting with RTL, through automatic insertion of power management logic based on UPF specifications. The Questa platform provides silicon-accurate simulation of isolation and retention protocols during power down/up, non-operational bias modes, and dynamic voltage scaling, as well as static and dynamic checks for power management functional correctness that pinpoint any failures to simplify debugging.
  • The FormalPro tool verifies the pre- and post-routed netlists against the RTL + UPF specification from which they were derived, to ensure that retention registers, isolation buffers, and level shifters are equivalent, as well as verifying logic equivalence.
  • The Olympus-SoC implementation system provides true multi-corner multi-mode (MCMM) optimization of timing, power, signal integrity and die size, and MCMM clock tree synthesis and optimization. The Olympus-SoC system provides UPF hierarchical low power automation with both top-down and bottom-up flows. It also provides a completely automated, multi-voltage flow with support for Dynamic Voltage and Frequency Scaling (DVFS) handles varying supply voltages and clock frequencies, as well as special power-related cells such as level shifters, isolation cells, and MTCMOS switches.
  • The TestKompress ATPG tool reduces power dissipation during all phases of scan test using a constant-fill decompressor, which reduces unnecessary logic transitions, and power-aware control of clock gates.

“Mutual customers of Mentor and TSMC continue to push the design envelope to create complex SoCs that require adoption of advanced, low-power technologies,” said John Lenyo, Mentor Graphics functional verification division general manager. “Our collaboration with TSMC gives design teams access to a comprehensive low-power flow that addresses the low-power challenges from design inception to tapeout.”

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:

(Mentor Graphics, Mentor, Questa, 0-In and TestKompress are registered trademarks and FormalPro and Olympus-SoC are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)


Mentor Graphics
Carole Dunn, 503-685-4716
Email Contact
Sonia Harrison, 503-685-1165
Email Contact

Review Article Be the first to review this article
Featured Video
NAND Hardware Engineer for Apple Inc at Cupertino, California
Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California
Technical Product Manager- SISW-EDA 238452 for Siemens AG at Fremont, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Upcoming Events
SEIA' 2021 at Palma de Mallorca Balearic Islands Spain - Sep 22 - 24, 2021
Strategic Materials Conference (SMC) 2021 at DoubleTree by Hilton san jose CA - Sep 27 - 29, 2021
MIPI DevCon 2021 at United States - Sep 28 - 29, 2021
Embedded Systems Week at Virtual Conference Virtual Conference - Oct 10 - 15, 2021

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise