SAN FRANCISCO — (BUSINESS WIRE) — September 22, 2009 — Intel Corporation executives today said Moore’s Law, driven by Intel’s advances in 32 and 22 nanometer (nm)-manufacturing technologies, is leading to a broader and faster pace of “innovation and integration.” Future Intel® Atom™, Core® and Xeon® processors and System on Chip (SoC) products will make computers smaller, smarter, more capable and easier to use. For example, among a number of other innovations on tap, Intel will integrate graphics into some of its future chip products for the first time ever.
“Over the past 40 years, the opportunities enabled by Moore’s Law have gone beyond just impressive performance increases,” said Sean Maloney, executive vice president and general manager of the Intel Architecture Group. “The rapidly increasing number of transistors and processor instructions we add have made possible the integration of more and more capabilities and features within our processors. This has driven an incredible amount of innovation throughout the industry, with the real winners being the consumers, gamers and businesses which buy these Intel-based computers.”
Next Generation Processors – Westmere and Sandy Bridge
In his Intel Developer Forum keynote, Maloney demonstrated a Westmere-based PC that showed a marked increase in responsiveness on simple, everyday tasks such as Web-surfing with multiple windows open.
Moreover, Westmere is Intel’s first 32nm processor, and historic in that it is the first-ever Intel processor to integrate graphics die right into the processor’s package. As well as supporting Intel® Turbo Boost technology and Intel® Hyper-Threading Technology, Westmere adds new Advanced Encryption Standard (AES) instructions for faster encryption and decryption. Westmere in on track with wafers already moving through factory floors for planned fourth-quarter revenue production.
After Westmere, Intel’s chip integration will continue with 32nm processors codenamed “Sandy Bridge.” Sandy Bridge features Intel’s sixth-generation graphics cores on the same die or silicon real estate as the processor core, and will include acceleration for floating point, video, and processor intensive software most often found in media applications. Maloney showed a Sandy Bridge-based system running a range of video and 3-D software to demonstrate the health of a far-future product line at its early stage.
Maloney demonstrated early silicon based on the “Larrabee” architecture, the codename for a family of future graphics-centric co-processors. He also confirmed that key developers have received development systems.
With the first product due next year, Larrabee takes the programmability of Intel Architecture and dramatically extends its parallel processing capabilities. This flexible programmability and the ability to take advantage of available developers, software and design tools give programmers the freedom to realize the benefits of fully programmable rendering and thus easily implement a variety of 3-D graphics pipelines such as rasterization, volumetric rendering or ray tracing.
Combined, PC users will experience stunning visual experiences on Intel-based PCs that incorporate this product. Maloney went on to demonstrate a real-time ray-traced version of the popular game “Quake Wars: Enemy Territory” running on Larrabee and Intel’s next-generation enthusiast gaming processor, codenamed “Gulftown,” which will carry the Core brand. While Larrabee silicon will initially appear in discrete graphics cards, the Larrabee architecture will eventually be integrated into the processor along with other technologies.
Maloney also provided attendees with a preview of Intel’s next-generation intelligent server processor, codenamed Westmere-EP, and Intel’s commitment to the high-end of the server market with its Xeon and Itanium processor families. Maloney discussed the unprecedented generational improvement that the forthcoming “Nehalem-EX” server processor will deliver, with performance improvements even greater than what the current Intel® Xeon® 5500 Series provided versus Intel’s previous chip generation.
Maloney described the convergence of compute, networking and storage in the data center, sharing the company’s vision of a converged datacenter IO fabric led by Intel 10GbE solutions. Intel also has a number of joint efforts with other industry leaders to deliver optimized platforms, systems, technologies and solutions to address the “hyper-scale” data center environments of the Internet and cloud services trend.
Maloney disclosed a new ultra-low-voltage Intel® Xeon® 3000 series processor featuring a TDP (Thermal Design Power) of only 30 watts. To complement the broad range of dense and power-optimized platform offerings, Intel also demonstrated publicly for the first time a single-socket “micro server” reference system which will help enable micro server innovation and future specification.
Maloney also described the just-disclosed “Jasper Forest” family of embedded processors as an example of extending the company’s popular Nehalem microarchitecture to new markets. Available early next year, Jasper Forest is designed for purpose-built storage, communications, military and aerospace applications, and will offer a new level of integration to save precious board space and power for these dense environments.
Finally, Maloney announced a new PC management tool using Intel® vPro™ technology. Keyboard Video Mouse (KVM) Remote Control enables IT personnel to investigate issues exactly as the user sees them, resulting in faster diagnosis, fewer desk side visits and added cost savings.
Intel Technology and Manufacturing – Almost 3 Billion Transistors on a Chip
In his keynote address, Bob Baker, senior vice president and general
manager, Technology and Manufacturing Group, underscored Intel’s
relentless pursuit of Moore’s Law and its benefits to PC users, and
provided more detail on the company’s milestone in 22nm process
technology. The company is the first to demonstrate working 22nm SRAM
and logic test circuits. The 364 million bit SRAM array includes 0.092
square micron SRAM cells and 2.9 billion transistors. These are the
smallest SRAM cells in working circuits reported to date.