Jasper Chief Architect Ziyad Hanna Presenting At IEEE High-Level Design Conference Nov. 6, San Francisco

WHO
Ziyad Hanna, Chief Architect and Vice President of Research, Jasper Design Automation

WHAT

Hanna will present an Invited Paper at the prestigious IEEE International High Level Design Validation and Test (HLDVT 2009) Workshop along with Professor Tom Melham of the University of Oxford. His paper, “A Symbolic Execution Framework for Algorithm-Level Modeling,” describes his Oxford PhD work.

WHEN

Friday, Nov. 6, 9:45am

WHERE
San Francisco, Grand Hyatt Hotel

WHY
The IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level. The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, synthesizing, and testing designs specified using high level descriptions, in an effort to address high level design, validation, and test issues concurrently. For more information and directions: www.hldvt.com/09.

About Jasper Design Automation

Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.




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