de facto Standard Verilog Parser Serves as Front End to Soon-to-be-Launched Next-Generation Floorplanner
ALAMEDA, Calif. — (BUSINESS WIRE) — March 31, 2010 — Verific Design Automation, supplier of de facto standard front-end software, today announced newly launched Parallel Engines Corporation has integrated its software into a toolset that merges semiconductor intellectual property (IP) and Electronic Design Automation (EDA) into one system.
Parallel Engines licenses Verific’s Verilog and register transfer level (RTL) elaborator to serve as the front end to next-generation floorplanning software that will be announced within the next several months.
George Janac, founder of Parallel Engines, as well as Chip Estimate, Silicon Navigator and High Level Design Systems, consistently works with Verific. “Verific may be the first vendor I call once we incorporate because it’s a company with first-rate products and excellent support. Its tools have been a key component within three different product lines at three different companies. Parallel Engines will utilize Verific in its upcoming IP/RTL Level, web-enabled floorplanner, aiding designers in physical semiconductor-IP integration.”
Michiel Ligthart, Verific’s chief operating officer, adds: “George Janac understands the concept of core versus context very well and applies it over and over again. Parallel Engines strength is in IP and floorplanning, while Verific’s is in RTL parsing.”
Verific’s software serves as the front end to a variety of Electronic Design Automation (EDA), semiconductor IP and Field Programmable Gate Array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.
About Parallel Engines
Parallel Engines is a privately funded company dedicated to the merging of Electronic Design Automation and semiconductor IP, targeting the front-end process from specification through IP-assembly to physical planning. The company delivers both web-based and engineering desktop solutions. Its web-based tools integrate the IP supply chain of more than 400 vendors delivering over 12,000 unique pieces of IP. Parallel Engines is headquartered at 10773 North Wolfe Road, Cupertino, Calif. 95014. Telephone: 408-257-3643. Facsimile: 408-257-3644. Email: Email Contact.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
Public Relations for Verific
Nanette Collins, 617-437-1822
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