vMAGIC - Automatic Code Generation for VHDL

Perhaps you know the situation where you find yourself adapting an old design for the thirty-second time, to reuse it in yet another project, just because generics can’t express what you want to do.  Or you want to provide an IP core with a lot more configuration options than you can sensibly handle with VHDL generics. Or you need to extract information from your designs and the existing tools just don’t do the trick. And you think there must be some kind of solution for this… and there is.

 

We were facing the very same problems in 2006 when we were creating a very general test framework for FPGA based digital hardware. There was a generic way to connect any design (in hardware) to a number of simulators, but the generation of the appropriate interface and bus decoder was very tedious work, especially when optimization techniques were involved. Thus we required a tool which could read an existing VHDL design and create interface designs to “wrap” the functionality, again in VHDL. So the vMAGIC library was born, which now integrates a complete VHDL parser, a high level API to analyze/modify/create the code, and a VHDL writer for code generation purposes.

 

The vMAGIC design flow usually, but not necessarily, comprises three steps. We briefly describe the flow using the bus decoder example: imagine a situation where you have an FPGA environment, which is connected to the host using some kind of bus interface. Now you want to be able to create bus decoders for every new design without writing the VHDL.  Instead you build a vMAGIC application: In the first step, your application reads the user design and a template containing static parts of the bus decoder. The parser creates an intermediate format which can easily be accessed using the vMAGIC API, allowing for operations such as entity.getPort().getSignals() or architecture.add(new Process()). Your application now analyzes the user design and creates an appropriate bus decoder; as you have used a template VHDL file, only the parts which are not already in the template have to be created using vMAGIC.  In the last step the intermediate format is transformed back to readable VHDL code, such that standard synthesis tools can process your design.  

 

The idea of using Java to create VHDL might seem strange at first, but there are a number of advantages in using it:

  • Powerful: Java delivers a powerful environment to easily create any kind of structure. Imagine a high performance, hard coded, pattern matching algorithm. Writing a generator which takes, e.g., a regular expression as an input will be much easier than hand coding a couple of these structures by hand
  • Correctness: Once your well written generator produces correct designs, it will do so for all times and all designs. No more searching for silly errors in your cores.
  • Fast: Obviously it takes some time to implement a code generator, but once you have done that, generating new hardware is a matter of seconds.

 

And there is more: we are currently working on a VHDL Linter based on vMAGIC, an XML input/output plugin and ultimately a powerful VHDL editor to give you all the features of the IDEs you know from the software realm. And all that for free under GPL/LGPL.

The project is hosted by sourceforge on http://vmagic.sf.net. Have a look at it and tell us what you think about it, we appreciate your comments!




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