"Verification is the bottleneck," remarks Dr. Andreas Veneris, president and chief executive officer (CEO) of Vennsa Technologies. "Deep in its core is a highly manual and time-consuming debugging task, a true nightmare for every engineer. In the past decade, several verification tasks have been automated, but debugging has all but been ignored. As design complexity increases, so does the pain of manual, GUI-based debugging. Our debug automation software changes that."
Vennsa's OnPoint automates the manual root cause analysis performed by verification engineers once a functional failure occurs. It picks up where simulation and formal verification tools leave off by automatically analyzing the problem and pointing to the exact lines of code where the failure can be fixed. This error localization process is performed with no intervention by the engineer.
According to many technology roadmaps, debugging accounts for approximately 60% of the verification process, adding weeks or months of extra labor per design cycle. It is one of the most time-consuming tasks in the chip design cycle. As the consumer product's life gets shorter and the cost of missing the market introduction gets higher, the delay associated with manual debug can undermine the whole business plan behind a product.
Locating and fixing bugs continues to be a mostly manual effort. These cyclical tasks are performed hundreds of times per design by multiple verification engineers and designers. Additional overhead is introduced as verification and design teams are sometimes geographically dispersed and not familiar with the intricate details of each other's work. Engineers must trace manually through signals, navigate the source code and stare at waveform viewers to understanding the source of failure with little automation.
OnPoint is a root cause analysis tool that locates the source of failures at the register transfer level (RTL) in assertions and stimulus with no user interference. It is based on scientific technology that spans over a decade.
Once verification fails, OnPoint reads the design and the counter example from the verification tool to automatically return the root cause of errors. In early evaluations, design teams confirmed that it can slash the manual debugging effort by weeks or even months.
Further, OnPoint can assist with debugging by fixing waveforms with insight on what correction is required and the exact cycles where the error is active during simulation. OnPoint can find all types of functional bugs in the RTL code, assertion or assumptions, including conceptual or high-level errors; state transition bugs; bugs in assertions, assumptions and constraints; incorrect assignments; wrong operations; wrong if/case conditions problems with module instantiation; or bad module wiring.
It includes support for the Verilog hardware description language, SystemVerilog, SystemVerilog Assertions, the property specification language (PSL) and the Open Verification Library (OVL). It runs on the Linux operating system.
OnPoint has been adopted by leading semiconductor companies in Japan and is being evaluated at several U.S. and Asian companies.
Vennsa will demonstrate OnPoint in Booth #250 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim, Calif. For more information, go to: www.vennsa.com.
Technology Roots and Founding Team
Vennsa Technologies, founded in 2006 by Dr. Andreas Veneris and Dr. Sean Safarpour, leverages more than 10 years of research and patented intellectual property (IP) from the University of Toronto. It employs a team of 14 technical and business development experts. Vennsa is privately held and funded.
Dr. Andreas Veneris, president and CEO, is a leading authority on circuit debugging and verification. As a professor at the University of Toronto, he has published more than 70 papers on debugging and delivered specialized in-house tools to many semiconductor companies. Previously, he was a visiting faculty at the University of Illinois at Urbana-Champaign, where he also obtained his Ph.D.
Dr. Sean Safarpour, chief technology officer and vice president of engineering, has extensive industrial and academic experience in hardware and software research and development. Prior to co-founding Vennsa, Dr. Safarpour held various ASIC and FPGA design and verification positions. He received his Ph.D. from the University of Toronto.
Lavi Lev, former CEO at Credence and Cadence executive vice president, is executive chairman of the board. Advisors include industry veterans Dr. Res Saleh, founder of Simplex, now Cadence; Dr. Masahiro Fujita from the University of Tokyo and former director at Fujitsu Labs; Dr. C.L. (Dave) Liu, who was on the faculty at MIT and the University of Illinois and later president of National Tsing Hua University; and Dr. Magdy Abadir of Freescale.
Vennsa Technologies Inc. is dedicated to the automation of debugging and error localization. Its breakthrough OnPoint tool is the industry's only automated debugging software that localizes the source of functional errors without any user guidance. When failures occur, OnPoint quickly identifies the root cause of errors and provides error fixes so the user can and remove the bugs. Vennsa is headquartered in Toronto, Ontario, Canada with dedicated sales force in US and in Japan. Telephone: (416) 829-0091. Email: Email Contact. Website: www.vennsa.com.
OnPoint is a registered trademark of Vennsa Technologies Inc. Vennsa Technologies Inc. acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
For more information, contact: Nanette Collins Public Relations for Vennsa Technologies (617) 437-1822 Email Contact