Mentor Graphics Publishes High-Level Synthesis Reference Book in Answer to Increasing Adoption of Technology

WILSONVILLE, OR -- (MARKET WIRE) -- Jun 09, 2010 -- Mentor Graphics Corp. (NASDAQ: MENT) today announced the availability of the "High-level Synthesis Blue Book," by Michael Fingeroff, technical marketing engineer in the High-level Synthesis (HLS) group at Mentor. The " High-level Synthesis Blue Book" is a comprehensive guide for designing hardware using C++ and is written for hardware and system designers who are currently using, moving, or planning to move to a high-level synthesis design environment that lets them reduce the time to verified RTL.

The "High-level Synthesis Blue Book" explains the fundamentals of high-level synthesis and the essential principles of C-based hardware design, progressing from simple concepts such as sequential logic design, to more complicated topics such as memory architecture and hierarchical sub-system design. All the concepts presented in the book have practical application for developing hardware, and are illustrative independent of whether a designer is working in pure ANSI C++ or in SystemC.

The concepts are thoroughly illustrated with numerous code examples and rich supporting graphics of hardware and timing diagrams. Starting from simple practical cases, the examples ultimately translate to much larger, more complex designs typical of today's multi-core SoC designs. Upon completion of reading the "High-level Synthesis Blue Book," a designer should be well on the way to becoming an expert in using high-level synthesis.

"After talking with hundreds of customers using HLS tools, and many RTL designers wanting to move to HLS, we decided there were obvious things we could do to help accelerate the adoption and use of high-level synthesis technology," said Simon Bloch, vice president and general manager, Design and Synthesis division at Mentor. "The 'High-level Synthesis Blue Book' provides a firm foundation for writing high-quality synthesizable C++ code including recommendations for achieving superior quality of results in hardware and good programming practices to ensure 'clean' code that passes compilation, execution, and RTL/C++ co-verification."

The release of the "High-level Synthesis Blue Book" is just one of the many activities engaged in by Mentor to help hardware designers adopt HLS technology. Other programs include an active HLS silicon vendor program, as demonstrated by the Catapult® C tool support for TSMC RF 11, the certification of multiple EDA vendor ESL flows, consulting services, extensive training, involvement in standards and a robust university program.

Interested in what's new in the Catapult C tool, including support for SystemC? Visit the Mentor booth #1383 at the Design Automation Conference (DAC), June 14 - 16, 2010, and register to attend the suite session titled: Catapult C Synthesis: A Game Changer for Full-Chip, High-Level Synthesis. For online registration prior to the conference visit: http://www.mentor.com/events/design-automation-conference/.

Availability
For a copy of the "High-level Synthesis Blue Book," visit: http://www.hlsbluebook.com/.

About Catapult C Synthesis
The Catapult C Synthesis tool automatically generates control and algorithmic RTL multi-block designs from pure ANSI C++ and SystemC sources. This process empowers designers to quickly achieve fully optimized and error-free hardware implementation. By accelerating time to verified RTL without sacrificing quality of results, the Catapult C tool provides the productivity boost required to tackle the design and verification challenges of modern ASIC design. The Catapult C tool has been recognized as the HLS market leader by Gary Smith EDA for three years in a row.

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics and Catapult are registered trademarks of Mentor Graphics Corporation. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners.)

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Carole Dunn
Mentor Graphics
503.685.4716

Email Contact

Ryerson Schwark
Mentor Graphics
503.685.1660

Email Contact 



Reviews:
Review Article
  • [censored], Write a Book Report For Me May 05, 2021
    Reviewed by 'Lincoln Bleakley'
    Hi, thanks for an interesting, informative, and very helpful post. I often study such materials, I read a lot of books, but analytics of books is difficult for me, it is easier for me to use https://edusson.com/write-my-book-report and trust the experts in this matter. I recommend this written service to you, who always writers take care of your book reports, everything will be done quickly and efficiently, try it now, leave an order and make sure that you can save time and get a quality product.

      Was this review helpful to you?   (Report this review as inappropriate)


For more discussions, follow this link …

 Advanced Asembly

Featured Video
Editorial
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
IBM’s 2nm chip; EDA updates; AI updates; acquisitions
More Editorial  
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Next Week’s Main Event: The ESD Alliance CEO Outlook
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating the UVM Register Abstraction Layer (RAL)
Jobs
Technical Product Manager- SISW-EDA 238452 for Siemens AG at Fremont, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
ASIC SoC Verification Engineer for Ericsson at Austin, Texas
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
ASIC Engineer for Juniper Networks at Sunnyvale, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Upcoming Events
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021
Verific: SystemVerilog & VHDL Parsers



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise