"We are very pleased with the Mentor solutions that have been incorporated into our first Analog and Mixed-Signal Reference Flow," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. "The unique capabilities provided by Mentor help ensure that our mutual customers are able to create high performance designs that will take full advantage of TSMC's process. Moreover, full compatibility and integration between the Calibre® platform and all other design flows minimizes the learning curve for designers, while allowing them access to an industry-leading verification solution."
The ICanalyst product provides a robust AMS functional verification platform for multi-process corner analysis and design document generation. With the tight integration with simulation engines and databases, the ICanalyst product delivers productivity improvements for analog/mixed-signal verification with its scenario manager and re-usable configurations. The Eldo® simulator handles netlists with large numbers of parasitic RC elements, and offers 3x speed gain with multi-threading technology for analog block level simulation. The ADiT simulator enables top level PLL simulation and 50x speed improvement over SPICE.
The new Calibre xACT 3D parasitic extraction tool delivers field solver level accuracy with the performance of a rule-based solution. This gives designers the quality extraction they need for sensitive analog circuits, such as convertors and matching circuits, and for critical digital nets. As part of the Calibre family, the Calibre xACT 3D product is not only a full-function extraction platform, it is seamlessly integrated with Calibre nmLVS to provide a complete solution for analog designers.
Mentor's Calibre PERC tool enables automated electrical rule checking and circuit verification to ensure designs meet TSMC's requirements in the area of analog layout guidelines. The product's unique ability to combine topological and geometric checking in a hierarchical design allows it to flag complex errors so designers can easily debug and improve overall circuit quality, making Calibre PERC the only product capable of doing these checks in TSMC's AMS 1.0 reference flow. As part of the Calibre platform, it is tightly linked to physical verification and parasitic extraction tools to ensure an efficient design flow.
The Calibre nmDRC and nmLVS products are also part of the TSMC 28nm AMS Reference Flow. Moreover, the Calibre platform is the physical verification platform used to validate TSMC PDKs (Process Design Kits), which provide the models used in their first AMS Reference Flow.
"As analog and mixed signal designs move to advanced nodes, it is critical that designers have an accurate and reliable simulation and verification environment to ensure their products will meet specs and be highly manufacturable while still hitting ever shortening design cycle times," said Walden C. Rhines, chairman and CEO, Mentor Graphics. "This is an area where Mentor shines with products that have proven their worth over many generations of IC development, making them key elements of both TSMC's AMS and digital reference flows."
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For more information, please contact: Gene Forte Mentor Graphics 503.685.1193 Email Contact Ry Schwark Mentor Graphics 503.685.1000 Email Contact