A unique and complete ESL / RTL front end design suite for ESL and RTL Front end Integrators, IP and SOC verification Engineers, Software platform Engineers
SOC Integrators and validation engineers will benefit from an automatic and certified top netlist code generation for both RTL and SystemC . A specific Tight Integration has been realized for Cadence Incisive simulator and Magillem Platform Assembly for smoothly switching from an abstraction level to another one.
This unique combination of a virtual platform tool and a state of the art RTL design entry allows more flexibility and power when designing new flows. In addition to the connectivity data, engineers can rely on an accurate description of system memory maps and registers. Verification files and drivers sequences can be automated and mutual customers have an opportunity to reduce their design and verification cycle.
"New design methodologies for building Hardware and Software involve concurrent development techniques and consolidation of design data. This demands a solid and open and flexible backbone. Magillem provides a unique production tool to capture and assemble ESL and RTL designs. This approach relies on simplicity, openness and scalability." says Cyril Spasevski, CTO Of Magillem
Simplicity : a common suite to capture ESL and RTL platforms, designed for System, Firmware, Verification and Hardware Engineers
Openness : IEEE P1685 IP-XACT xml format is used to preserve integrity
Scalability : tools need to capture and update information focus on connections and registers
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