UVM represents the culmination of Mentor Graphics' effort to drive the development of an open verification environment that would promote better tool interoperability and verification data portability that began with the release of the first open-source Advanced Verification Methodology (AVM). AVM became the foundation for initial industry collaboration and fostered the development of the Open Verification Methodology (OVM) upon which the UVM is based.
"Mentor recognized early that only an open source verification methodology would provide users the ability to write fully portable and reusable verification components," said John Lenyo, general manager, Design Verification Technology division at Mentor Graphics. "We are proud to see that the technology we first developed in AVM and refined in OVM now continues as the core of UVM."
The Questa advanced functional verification platform offers native support for UVM by virtue of its industry-leading support of the IEEE Std 1800 SystemVerilog standard on which UVM is based. This support includes comprehensive language feature support, native single-kernel simulation and full functional debug of SystemVerilog and UVM.
The Questa Verification IP library has added native support for UVM. This allows users of UVM access to a comprehensive verification IP (VIP) solution that supports a wide range of industry-standard protocols without the need for any manual conversion, interoperability, or wrapper layers. The Questa Verification IP library dramatically improves verification coverage and helps speed the functional verification of integrated circuits (ICs) using industry-standard protocols. As a result, users of the Questa Verification IP library components can expect to see an improved time to market and a higher quality product.
The Veloce emulation platform fully supports the UVM. The primary advantage to companies using both the UVM/OVM and the Veloce platform is the ability to use a single transaction-based testbench for both simulation and emulation -- two technologies that are critical to the functional verification of large, complex system-on-chip (SoC) designs.
The Certe Testbench Studio tool helps verification engineers harness the power of UVM by guiding the development of testbenches and registers that are correct-by-construction. The Certe Testbench Studio tool also delivers deep insight into the testbench construction and functionality via UVM testbench visualization, multiple class relationship views, full testbench object browsers, and register management. The Certe Testbench Studio tool enables rapid creation, complete understanding, and documentation of UVM testbenches for the most complex designs.
UVM Based on OVM
UVM 1.0 gains its leverage being based on OVM 2.1.1. OVM users will discover that great attention has been paid to backward compatibility to make it easier to migrate to UVM when ready. Conversion scripts take OVM 2.1.1-based code and convert it to UVM making it easy for current OVM users to adopt UVM at their own pace.
UVM is available from Accellera at www.accellera.org. OVM users can download the UVM kit from www.uvmovmworld.org where additional help and information specific to current OVM users can help them accelerate the adoption of UVM.
About Mentor Graphics
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(Mentor Graphics, Questa, and Veloce are registered trademarks, and Certe is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
For more information, please contact: Carole Dunn Mentor Graphics 503.685.4716 Email Contact Ry Schwark Mentor Graphics 503.685.1660 Email Contact