Magillem and Cadence expand System Realization Alliance collaboration: Both define IP-XACT based methodology for IP packaging and assembly from virtual prototypes through RTL

Paris, France, 13 June 2011,- Leveraging years of experience in their domain, Magillem, the leader of IP-XACT based solutions and Cadence Design Systems are collaborating to bring a complete methodology and associated technologies for IP packaging and assembly from virtual prototypes through RTL.

“New design methodologies for building hardware and software involve concurrent development techniques and consolidation of design data, as well as advanced prototyping,” says Cyril Spasevski, chief technology officer at Magillem. “Providing a single state-of-the-art platform assembly with a user-friendly GUI combined with the new Cadence Virtual System Platform, part of the Cadence System Development Suite, will create a unique and complete system-level-through-RTL front-end design environment for front-end integrators, IP and SOC verification engineers, and software platform engineers.”

Magillem, a member of the ARM Connected Community, has successfully completed an integration of the new Virtual System Platform from Cadence with ARM Cortex models. Design of ESL platforms fully benefit from advanced features of the RTL Platform Assembly. Management of all contributors to the platform allows for a coherent data update system and incremental synchronization in concurrent mode. Registers capture and management, as well as components configuration, provide a comprehensive description of the platform hardware. Code generation for firmware, OS and boot is then automated for productivity gains thanks to Magillem’s dedicated template-based Generator Studio. Software customizations and derivatives packages can be streamlined and linked to a reference virtual platform.

Magillem, one of the early sponsors of IP-XACT, has earned a well-deserved reputation in the ESL/ RTL front end of design flows. One of the key steps of a flow is the preparation of components libraries for their integration in a system. Various strategies translate into wide gaps in the resulting assembly time gains. The goal is to automate connection rules, but also and maybe more importantly, the IP update rules: parameters, configurations, connections of IP instances. Those mechanisms are only possible with a powerful packaging of the IPs: Magillem IP Packager (MIP), provides these capabilities, and is the only one to address the need for the demands of the markets largest platforms.

Packaging of IP is a critical step to deploy an IP Reuse methodology. A key factor of a successful packaging solution is the expected quality improvement and time savings in the Verification flow. Productivity and capacity benefits can be achieved with a coupling of an IP packaging solution for automation preparation, with simulation flows, in this case Cadence Incisive Verification Platform and Virtual System Platform, especially for very large SoC platforms.

“The announcement of the Cadence Virtual System Platform is a significant advancement by Cadence and expansion into the software development market,” says Michael McNamara, vice president and general manager, Systems Level Design, Cadence. “The challenge of developing and verifying these complex systems requires a closely aligned solution for managing the IP process in concert with simulation and verification.”

About Magillem
Magillem, a board member of ACCELLERA, has developed an easy to use, IP-XACT based state-of-the-art platform solution to cover electronic systems design flow challenges in a context where complexity, interoperability and design re-use are becoming critical issues to manage design cycle time of SOC.
Company is Headquartered in Paris, France, with offices in New York, USA and Tokyo, Japan. Customers include the first tier SoC manufacturers worldwide.
Magillem is a public company traded on the Euronext Free Market.

About IP-XACT / IEEE 1685™
IEEE 1685™, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows," describes an XML Schema for meta-data documenting Intellectual Property (IP) used in the development, implementation and verification of electronic systems and an Application Programming Interface (API) to provide tool access to the meta-data.
IP-XACT was created by the SPIRIT Consortium, now part of Accellera, as a standard to enable automated configuration and integration through tools. 150 industrial companies and organizations are members. The goals of the standard are: to ensure delivery of compatible component descriptions from multiple component vendors, to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments), to describe configurable components using metadata, and to enable the provision of EDA vendor neutral scripts for component creation and configuration.

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