Introduction to Lynguent Part II
The initial EDA Weekly article on Lynguent, Inc. appeared in EDAcafe.com on Monday November 15, 2010, and it has appeared every day since. You may refer to Lynguent Part I at the following URL:
During the initial interview with Lynguent representatives on September 10, 2010 at the Claremont Resort & Spa, it became clear to this writer that one installment of EDA Weekly would prove insufficient to adequately describe even the minimum attributes of this Portland, OR privately-held EDA entity.
Thus Lynguent Part I was devoted to briefly introducing the new CEO Sam Young and the founder and current CTO Martin Vlach, and to hinting at Lynguent’s specialty & raison d’être: To tackle one of the most difficult and ongoing problems in EDA -- dealing successfully with analog and analog mixed signal (AMS) systems, which are often subsystems of a companion digital systems product. As mentioned, “dealing successfully” this time around meant reaching a goal of a 10 to 1 improvement or more, compared to trying to write an analog model or AMS model purely with an HDL. The market opportunity for this nine year old company was also outlined.
This December 13, 2010 issue of EDA WEEKLY will first expand on the technical approach that Lynguent has taken in its software products to address the challenges of analog and analog mixed systems (AMS). We will name this portion Lynguent Part II Section One.
Secondly, we will provide more details on the backgrounds of several key Lynguent cognoscenti. We will cleverly name this second portion Lynguent Part II Section Two.
Lynguent Part II Section One:
Picking up on the introductory dialogue in the Lynguent Part I posting of November 15, 2010, it bears repeating what we had learned about the Technical Specialty of Lynguent at the Claremont luncheon: Starting in 2004, Dr. Martin Vlach and his Lynguent team had decided to tackle one of the most difficult and ongoing problems in EDA -- dealing successfully with analog and analog mixed signal (AMS) systems, which are often subsystems of a companion digital systems product. As mentioned, “dealing successfully” this time around meant reaching a goal of a 10 to 1 improvement or more, compared to trying to write the analog model or AMS model purely with an HDL.
That was when the writer asked Dr. Vlach, “Please walk us through the first few years of Lynguent activity from 2004 on.”
Martin had continued as follows: Lynguent began with the premise that the design and verification of 100% digital semiconductor chips was and is already well supported in the marketplace by the use of models written in either Verilog® (C) or VHDL (D). There are also good tools available that convert a model used at one stage of the digital design to a new model to be used at the next stage. Examples of such tools are high level synthesis, Register Transfer Level (RTL) synthesis, and physical synthesis tools.
Note: Capital letters in parentheses and numbers in brackets refer to Definitions and Footnotes, respectively, included at the conclusion of this month’s EDA WEEKLY.
Verification is mostly done by applying suitable test vectors to digital models, although in some situations FastSPICE (E) simulations may be done. A single simulation using all-digital models is reasonably fast, so the time to complete verification is largely dependent on the number of test vectors. So purely digital design and verification is already a well-served market.
Conversely, analog and mixed-signal (AMS) chips are still much more difficult to design and verify, and no general methodology seems to have become available (until Lynguent).
The main reasons were and are:
- Digital designers often do not understand the analog design issues, and vice versa. As a consequence, the analog and digital portions of a design are usually done independently and brought together rather late in the design process, leading to costly redesigns and delays if analog and digital don’t match up.
- There are no synthesis tools for AMS. Models needed at different stages of the design must be written manually, often by analog designers who are not comfortable working with a hardware description language (HDL).
- Verification that includes AMS models is inherently slow due to the involvement of an analog solver. Methodologies to speed this up are often proprietary and application specific. They include creating behavioral models whose parameters are tuned such that the model behavior matches that of the transistor level design
So the creation of suitable AMS models remained a major bottleneck in an AMS design. Such models are also needed in various forms (usually at different levels of abstraction) throughout the design phase and also to speed up verification. Additionally, meaningful verification requires an ability to tune the behavior of a model to match that of the transistor design. By providing unique products that breakthrough this bottleneck, Lynguent can enjoy an enviable position in its market niche.
The above was a review of the background dialogue contained in Lynguent Part I. We now proceed to new technical details.
AMS models have traditionally been written directly in the HDL using a text editor. Each model is a programming project, and the only tool available for this task has been the text editor. Although some advanced editors offer syntax directed editing for HDL’s, several difficulties remain:
- The model writer must have a basic understanding of the concepts supported by the HDL. This understanding can only be gained by adequate training and experience, and if unused it tends to become stale quickly.
- The requirement of HDL knowledge suggests that models should be written by specialized modeling engineers. This has two drawbacks. First, a dedicated modeling engineer likely will support more than one design team and will therefore not be intimately familiar with the design. Second, sharing of a modeling engineer between design teams may quickly lead to unavailability of the engineer when a design team needs the help.
- Writing an HDL model of an AMS device is a difficult task in general. Even for simple models it is not easy to get it right, in particular when starting the model from scratch. There are two reasons: keeping perspective of the model becomes increasingly challenging when the model grows because the HDL statements may have little relationship to the actual device, and writing an efficient model requires familiarity with aspects of analog simulation and in particular the analog solver.
- Model maintenance is difficult, particularly if different people work on the same model over time. Even if comments have been used, it is often difficult to understand what a specific statement does and why it is there.
- The complexity of many models prevents their reuse because the work required to make the model reusable is not cost effective. The result is that models are typically written from scratch or derived from existing models. In the latter case the model may be inefficient because the model writer may easily overlook that certain portions of code are no longer needed.
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-- Russ Henke, EDACafe.com Contributing Editor.