NXP Secures the Edge with Two Industry-First Multi-Core Cortex-M33 Solutions

GEO Semiconductor Selects Cadence Tensilica Vision P5 DSP for Their Most Advanced Automotive Smart Viewing Camera Processor

Media Alert: Cadence to Showcase Verification Suite at DVCon 2018

Cadence to Showcase Verification Suite at DVCon 2018

Cadence’s Lip-Bu Tan to Present at Morgan Stanley TMT Conference

NetSpeed Collaborates with Cadence to Optimize IP for Advanced Automotive SoC Designs

Paul Cunningham, Corporate VP and GM Cadence

Yoan Dupret, Managing Director Menta

Stephen Douglas, Head of 5G Strategy Spirent

EDACafe Editorial by Roberto Frazzoli Concerns over Nvidia-Arm deal; ISSCC innovations; DAC postponed to December

IC Insights by IC Insights TSMC Ranks in Top-10 For Capacity in Three Wafer Size Categories

Embedded Software by Colin Walls Variable declarations in C – plenty of pitfalls

Agnisys Automation Review by Anupam Bakshi AUGER: Celebrating Our Users

EDACafe Editorial by 2021 EDACafe Predictions Atmosic Technologies Electronics Design Industry Predictions

Staff SerDes Applications Design Engineer for Xilinx at San Jose, California

SerDes Applications Design Engineer for Xilinx at San Jose, California

Circuit Design & Layout Simulation Engineer - Co-Op (Spring 2021) for Global Foundaries at Santa Clara, California

Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California

ASIC Engineer for Amazon at seattle, Washington

Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California

DVCon U.S. 2021 at Virtual - Mar 1 - 4, 2021

IPC APEX EXPO 2021 Goes Virtual at - Mar 8 - 12, 2021

ISQED'21 - 22nd International Symposium at POB 607 Los Altos CA - Apr 7 - 9, 2021

ADAS Sensors 2021 at The Henry Hotel 300 Town Center Drive Dearborn MI - Apr 7 - 8, 2021