S2C Announces Next-Gen Prodigy MDM Pro to Simplify and Speed Up FPGA Prototyping Debug Process

S2C Raises the Bar for High Capacity, High-Performance FPGA Prototyping with New Prodigy Logic Matrix Family

S2C Accelerates Billion Gate FPGA Prototyping with Xilinx Virtex UltraScale+ VU19P Based Systems

S2C and Mirabilis Design Teamup to Deliver a Heterogeneous Solution for SoC Architecture Exploration and Verification

S2C Launches Prodigy(TM) S7 Series Logic Systems Based on Xilinx UltraScale+ FPGAs

S2C Launches Prodigy(TM) S7 Series Logic Systems Based on Xilinx UltraScale+ FPGAs

Michael Munsey & Brad Hart Perforce

Hitendra Divecha & Brandon Bautz Cadence

IPC APEX EXPO 2021 is the place to be...from wherever you are! IPC APEX

EDACafe Editorial by Roberto Frazzoli Nvidia’s datacenter CPU; fast AI training on x86; Siemens acquires OneSpin; EDA Q4 results

IC Insights by IC Insights Chinese Companies Hold Only 5% of Global IC Marketshare

Bridging the Frontier by Bob Smith, Executive Director What’s on Tap from the ESD Alliance? Plenty! Read On …

Aldec Design and Verification by Farhad Fallahlalehzari How does the Mars Perseverance rover benefit from FPGAs as the main processing units?

Agnisys Automation Review by Anupam Bakshi Automating IP and SoC Development

Staff SerDes Applications Design Engineer for Xilinx at San Jose, California

Pre-silicon Design Verification Engineer for Intel at Santa Clara, California

SerDes Applications Design Engineer for Xilinx at San Jose, California

Sr Engineer - RF/mmWave IC Design for Global Foundaries at Santa Clara, California

Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California

Business Operations Planner for Global Foundaries at Santa Clara, California

Simulation World at United States - Apr 20 - 21, 2021

Virtual ASMC 2021 at United States - May 10 - 12, 2021

DVCon China 2021 at Shanghai China - May 26, 2021

CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021