Avery Design Enhances Insight for Reachability Analysis, Lower Power Verification, and RT-Level DFT Analysis

During DAC, EVE to Highlight ZeBu's Infinite Verification Possibilities, STMicroelectronics' Use of ZeBu

Vennsa Technologies Sets Sights on Moving Chip Verification Beyond Debug

Real Intent Showcases EDA Tools for Bridging the Verification Gap, Participates in Workshops, Presents at Verification and Test Forum at 47th DAC

NVIDIA Extends Breker Verification Deployment to Next Generation GPU

EVE Adds Support for TLM-2.0 to ZeBu Hardware-Assisted Verification Platforms

Geir Eide, Director Mentor, a Siemens business

Brian Faith, President & CEO QuickLogic

Palladium Z2 and Protium X2 Cadence

EDACafe Editorial by Roberto Frazzoli Nvidia’s datacenter CPU; fast AI training on x86; Siemens acquires OneSpin; EDA Q4 results

IC Insights by IC Insights Chinese Companies Hold Only 5% of Global IC Marketshare

Bridging the Frontier by Bob Smith, Executive Director What’s on Tap from the ESD Alliance? Plenty! Read On …

Aldec Design and Verification by Farhad Fallahlalehzari How does the Mars Perseverance rover benefit from FPGAs as the main processing units?

Agnisys Automation Review by Anupam Bakshi Automating IP and SoC Development

SoC Physical Design Engineer for Qualcomm at Austin, Texas

SerDes Applications Design Engineer for Xilinx at San Jose, California

Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California

Circuit Design & Layout Simulation Engineer - Co-Op (Spring 2021) for Global Foundaries at Santa Clara, California

Pre-silicon Design Verification Engineer for Intel at Santa Clara, California

Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California

Virtual ASMC 2021 at United States - May 10 - 12, 2021

DVCon China 2021 at Shanghai China - May 26, 2021

CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021

DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021