You’ve talked a lot about “timing” and “RTL” but these days it seems that “power” is one of the big issues. What are you capabilities there?
Yes, power is a huge issue and one of the challenges is that power is mostly a chip level problem. Design teams care about how long the battery will last in a phone, system engineers care about whether they can get away with a cheap package, avoid a fan, and so on. Nobody cares really about how much power individual blocks take, apart from perhaps some local thermal issues. It is a weakness of traditional tools that the power budget has to be divvied up without really any rationale for how to do it.
We operate at the chip level, which means we can handle power at the chip level and make tradeoffs across the whole design. It is easy to change the value of some islands and re-synthesize the entire design in a few minutes and immediately see the results. With a traditional approach that might take a week of work. In practice, the early traditional power budgets got cast in stone since they were so difficult to change, which can then lead to last-minute crises when some of them turn out to be impossible to meet.
What has been Oasys’ biggest challenge?
(This was where we could really see Paul warming to his reply):
“We are competing in a mature market, in the sense that everyone already has a tool that does something similar to what we do. We have to deliver a solution that is as reliable as the competition and fits into existing flows before anyone even considers whether our results are better.
That was a lesson we learned back at Ambit. If your netlist is not correct, nobody cares about the performance. If you can’t read the library correctly, you don’t get to compete.
Another challenge is making it so that the technology is easy to adopt. Synthesis sits at the heart of everyone’s design flow, not in a little niche that only a couple of experts need to concern themselves with. So making RealTime Designer as painless as possible to get started with has been very important, as does having a team of superb AE’s to train customers and to cope with the inevitable issues that come up as the tool matures.
The investment environment has had an obvious impact. Venture capital for EDA is pretty much non-existent (these days) and I don’t think that is suddenly going to change. It’s a new reality and we were forced to do things differently. As a result, we are working with less than we would have if we had started Oasys 10 years ago. Magma and Monterey both raised around $100 million in venture capital, and that is not going to happen again. We would never have needed that amount of capital, but even relatively small amounts of VC money are impossible today. That means less money, fewer engineers and a longer development time-line.
Nobody embarks on a startup thinking it’s a six-year endeavor just to get to market, but that’s the reality we faced. On the other hand, it did allow us to focus on maturing the product before announcing the product and/or company.
When we started, we had a different perception than we have now. With my background from Ambit, I knew what it would take to build things from scratch, but we were still counting on the funding to be there. In the end, scarce funding was actually a blessing because we were forced to do more with less. It was a core team that worked on the technology from the ground up rather than having some ideas, build something and then have a big team work it out. In the end, it has helped the technology mature in the way it did because it was a technology completely different from what we had ever done before. There is a lot of satisfaction that comes from working with a small team of very knowledgeable and productive engineers.
However, it definitely took longer to develop the technology because of a lack of funding. It took us three years to get to a point where we could start engaging with some design teams. However, when we did, we realized that we had something different that was even better than we had imagined.
We started with a focus on how to combine RTL and gate-level synthesis in a unique way that basically gets better quality results. As we put this technology together, we realized that working on a higher level of abstraction was the right thing to do. Making these decisions much earlier at RTL is the way to go rather than going down to a gate-level netlist and doing a lot of lower level optimization. The speedup we got with that approach and how we built out the technology allowed us to run much bigger blocks, bigger designs and get the quality results we were looking for.
I don’t want to imply that the challenges are behind us. Our biggest challenge today is probably that we need to support all our initial customers and make them successful. This requires our AEs and our engineering team to be responsive. It is critical that we don’t take on customers faster than we can make them successful.
You never get a second chance to make a (good) first impression; that quote is attributed to both Irish writer and poet Oscar Wilde and American humorist Will Rogers, and it readily applies to EDA. In this industry, companies get only one chance to show that their tool is something that a mission-critical design can use.
With the new investment from Intel Capital and Xilinx, our focus today is to continue to build success in the marketplace through solid engagements with customer design teams and get our technology adopted in their production flows.”
A perfect place to end a great interview!
 The writer first become acquainted with Nanette Collins telephonically in 2010 when she worked with Lauro Rizzatti of EVE on one of the early EDA WEEKLY interviews the writer did with the founder of EVE’s North American office in San Jose, CA.
Later, Nanette was instrumental in encouraging Lin Hong and Jonah McLeod of Kilopass Technology to submit the first guest article in the January 10, 2012 EDA WEEKLY, while the latter was otherwise devoted to “Blurring the line between EDA and Test.”
The Kilopass guest article was entitled, “Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown.”
Subsequently, Nanette assisted in obtaining Breker Verification Systems’ participation in the more recent EDA WEEKLY posting of February 06, 2012 entitled, ”Silicon Valley – EDA Magnet,” in a similar role that Georgia Marszalek played in helping to gain the cooperation of Silicon Frontline for the same two-part article penned by yours truly: