Xilinx Returns to DAC Asking - Why ASIC When You Can Go All Programmable?

Xilinx exhibits for first time since 2002 to mark FPGA transition to All Programmable devices and the introduction of the Vivado Design Suite as a bridge from ASICs

SAN JOSE, Calif., May 23, 2012 — (PRNewswire) — Xilinx, Inc. (NASDAQ: XLNX) today announced participation at the Design Automation Conference (DAC) in San Francisco from June 3 - 7, 2012, including its first booth exhibition in 11-years where the new Vivado™ Design Suite will be showcased. As the costs and risks associated with application-specific devices can only be justified for a short list of ultra-high volume commodity products, programmable platforms have become the only viable means for meeting increasingly stringent product requirements – cost, power, performance, and density – begging the question: Why ASIC When You Can Go All Programmable?

What:

49th Design Automation Conference (DAC) 2012

Where:

San Francisco, CA, Moscone Center, Booth #730

When:

Exhibits: June 4-6, 2012


Conference Program: June 3-7, 2012

At 28nm, Xilinx has moved well beyond its programmable logic origins to develop All Programmable devices going far beyond traditional programmable logic to enable both hardware and software programmability, incorporate both digital and analog mixed-signal functions, and allow new levels of programmable interconnect within monolithic devices and multi-die 3D ICs. The Vivado Design Suite was developed from the ground up to enable the next decade of design with these All Programmable devices, and to create a powerful bridge from the ASIC world. The Vivado Design Suite is a system and IP-centric, next generation design system addressing the productivity bottlenecks in system level integration and implementation. Visitors to the Xilinx booth will learn how the Vivado Design Suite increases programmable design productivity up to 4X, lowers design costs and speeds time to market for the most highly integrated hardware and software-programmable designs. They will also see how the Vivado Design Suite supports ASIC design standards for IP metadata, IP interfaces, design tools, and a growing breadth of IP and design tool solutions from Xilinx Alliance Program providers.

Xilinx experts will discuss these topics and more through the following booth demonstrations, deep-dive technical sessions, and conference panels:

In-Booth Technical Sessions
Reserve a seat today for these sessions at: www.xilinx.com/DAC2012

  • Vivado Design Suite Overview - The new Vivado Design Suite accelerates integration and implementation by 4x over traditional design flows, reducing cost by simplifying design and automating – not dictating – a flexible design environment.
  • Vivado IP and System-Centric Design - The Vivado Design Suite is an IP and system-centric design environment comprised of the Vivado IP Integrator - an interactive design environment enabling creation and verification of a hierarchical system by graphically connecting IP cores provided by Xilinx, third parties or proprietary IP using interface level connections, and the Vivado IP Packager which enables Xilinx, third party IP providers and end customers to package a core, module or completed design with all constraints, test benches and documentation.
  • Vivado High-Level Synthesis - Vivado High-Level Synthesis accelerates design implementation by directly targeting C, C++, and SystemC specifications into FPGAs without manually creating RTL.
  • Vivado Implementation & Analysis - The Vivado Design Suite shared scalable data model is architected to enable extensive cross-probing between design sources, schematic views, hierarchy browsers, design reports, messages, floor plan and Device Editor views. This unique capability enables faster debug and timing closure by providing graphical feedback to identify design issues at each phase of design.

In-Booth Exhibition Demonstrations
All Vivado Design Suite demonstrations use either the Zynq™-7000 extensible processing platform or 3D IC enabled Virtex®-7 2000T device to showcase capabilities. For each hardware platform, Xilinx will demonstrate:

  • Vivado IP Integrator - An interactive design and verification environment enabling creation and verification of a hierarchical system by graphically connecting IP cores provided by Xilinx, third parties or proprietary IP using interface level connections.
  • Vivado Flow Implementation - Vivado Design Suite provides early access to critical design metrics such as power, timing, and resource utilization with increasing accuracy as the design progresses through the elaboration, synthesis, and placement and routing processes.
  • Vivado High-Level Synthesis - Vivado High-Level Synthesis accelerates design implementation by directly targeting C, C++, and SystemC specifications into FPGAs without manually creating RTL.

Xilinx Conference Participation
Tuesday, June 5

Wednesday, June 6

Thursday, June 7

About Xilinx
Xilinx is the world's leading provider of All Programmable technologies and devices, going beyond traditional programmable logic to enable both hardware and software programmability, integrate both digital and analog mixed-signal functions, and allow new levels of programmable interconnect in both monolithic and multi-die 3D ICs. The company's products are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com .

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