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NEWS from SpringSoft
SPRINGSOFT SHOWCASED ITS LATEST GENERATION CHIP DESIGN AND VERIFICATION TECHNOLOGIES AT 49TH DAC
On May 29, 2012 SpringSoft, Inc., asserting its identity as a global supplier of specialized IC design software, confirmed that it planned to host a series of activities at 49th Design Automation Conference (DAC) in San Francisco, CA, June 4 through June 6, 2012, that would feature and did feature the next-generation of its award-winning Verdi3 Automated Debug Platform and Laker3 Custom IC Design product family. SpringSoft also sponsored numerous annual DAC programs and industry consortium events in collaboration with other EDA and semiconductor leaders and standards groups.
At this year’s DAC, SpringSoft’s focus on delivering ‘Innovative Solutions, Interoperable Platforms and Intelligent Choices’ was highlighted through interactive demonstrations of the latest chip design and verification solutions in its Exhibit Booth #1030. In addition, SpringSoft’s DAC booth was the venue for the inaugural VIA Exchange Pavilion showcasing third-party tool and flow integrations with Verdi ecosystem partners that address key pain points in the chip development process and emerging technologies, including the creation, analysis, and debug of verification intellectual property (VIP), BIST, assertions, and DFT as examples.
At SpringSoft’sDAC Booth
SpringSoft demonstrated products that make it easier for engineers to do more functional verification in less time in the face of increasing complexity of multiple methodologies, languages, and abstractions:
- NEW Verdi3 Automated Debug Platform delivers performance and capacity gains and enables users to personalize, customize and enhance the interoperability of its open debug cockpit.
- Certitude™ Functional Qualification System, said to advance the state of the art in functional qualification of complex simulation and formal verification environments and critical sign-off flows.
- ProtoLink Probe Visualizer provides debug platform for FPGA prototype boards that is said to increase real-time design visibility by at least 1000X and integrates Verdi platform to accelerate debug across multiple FPGAs and multiple pre-fab or custom-made boards.
Demonstrations were conducted of SpringSoft’s Laker™ Custom IC Design solutions for analog, mixed-signal and custom digital design, claiming superior productivity and unmatched interoperability:
Laker3 Custom Design Platform optimized for OpenAccess performance and interoperability in
28 and 20-nanometer flows with the Laker Advanced Design Platform (ADP), Laker Custom Layout Automation System, Laker Custom Digital Place and Laker Custom Digital Route tools.
- NEW Laker Analog Prototoyping tool automates the process of analyzing advance process effects and generating constraints to guide circuit layout. First tool of its kind to offer automated constraint generation, layout exploration and rapid implementation in a unified flow.
- Laker Blitz Chip-level Editor provides fast import, editing and export of large GDSII data files required at process nodes for chip finishing applications, such as IP merging, SoC assembly and full-chip DRC.
SpringSoft also conducted other activities at DAC
- DAC User Track Session, Poster Session 2U.25: “LDE (Layout Dependent Effects) Aware Design Solution in Advanced Technologies” presentations by SpringSoft and TSMC on Tuesday, June 5, 2012
- IPL Alliance 6th Annual Luncheon: “Reaping the Benefits of iPDKs” on Tuesday, June 5, 2012
- Accellera Systems Initiative Luncheon: “Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard” on Wednesday, June 6, 2012
TSMC DAC Theatre (#2430): “LDE-aware Analog Layout” presentation by Dave Reed, SpringSoft 4th Annual “ I Love DAC” 2012, sponsored by SpringSoft, Atrenta, and Cadence.
On May 23, 2012 Synopsys, Inc. (NASDAQ: SNPS), calling itself a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, reported results for its second quarter of fiscal year 2012, the quarter corresponding to nominal Q1 2012 for EDA Commentary purposes.
For nominal Q1 2012, Synopsys reported revenue of $432.561 million, compared to $393.670 million in year ago nominal Q1 2011, an increase of “only” 9.88%. [But that 9.88% adds nearly $39 million in revenue!].
"We delivered strong results in the second quarter, and are raising annual guidance to reflect both the robustness of our base business and the rapid integration of Magma," said
Geus, chairman and CEO of Synopsys.
"Electronic design automation is the key technology that enables the development of electronics around the world. Synopsys is leading the way – with state-of-the-art products and support, and the vision and resources required to help take our customers to the next level of success."
On a generally accepted accounting principles (GAAP) basis, net income for nominal Q1 2012 was $21.0 million, or $0.14 per share compared to $81.1 million, or $0.53 per share, for Q1 2011. [Writer’s Comment: However, net income for last year’s nominal Q1 2011 included a one-time $32.8 million, or $0.21 per share, tax
benefit associated with a settlement with the IRS for audits for fiscal years 2006 through 2009. The comparison of these two quarters is futher warped by the fact that net income for Q1 2012 included $30.2 million of
costs associated with the acquisition of Magma Design Automation. Still these benefits and costs are real; the message here is that one cannot make a value judgment based on numbers for any single quarter].