Calling all IP core designers, users, and IP ecosystem providers to plan and participate
LOUISVILLE, Colo. — (BUSINESS WIRE) — November 21, 2014 — After a successful launch of the Intellectual Property (IP) Track at The Design Automation Conference (DAC) last year, the premier conference devoted to the design and automation of electronic systems is pleased to announce the IP call for contributions for DAC 2015. The DAC IP Track brings together the users and the creators of IP to discuss both the benefits and challenges of using IP to accelerate the development of new electronics devices, as well as improving the quality of the devices. This Track provides educational and networking benefits for IP core designers, users, and IP ecosystem providers. The 52nd DAC will be held at the Moscone Convention Center in San Francisco, California from June 7 - 11, 2015.
“We were extremely pleased with the participation and level of content presented last year at the IP track and know this year will once again surpass expectations,” said Michael “Mac” McNamara of Adapt-IP and the IP Chair for DAC 2015. “Semiconductor design IP providers, IP users and designers of tools that automate the assembly and verification of SoCs built with IP, as well as the providers of embedded software will once again have an opportunity to network and learn from each other.”
The IP Track provides an opportunity for experts in the field to deliver presentations and/or poster sessions on IP related topics; and to host panels and invited talks on timely IP related issues. The DAC IP Track Committee will consider favorably proposals that fit into our session matrix which address some part of the Internet of Things (IoT) marketplace.
The 2015 DAC IP track will include five 90 minute sessions, and one Poster Session, as follows:
- Low Power IP
- IP Implementation
- IP Subsystems and Integration
- Verification IP
- IP Strategies and Management
- IP Poster Session
The IP Track specifically seeks contributions from system engineers, hardware designers, embedded software developers, application engineers, and vendor/customer teams. Documented tool use may target electronic design and system design at all levels of abstraction and across all application domains.
Submissions may describe any aspect of the design, use, verification, selection process, assembly process and export process of intellectual property cores. Tools can be from EDA vendors or developed in-house, while flows can be built around a single tool or multiple tools:
1. IP Provider (IPP): Providers of third-party IP and are invited to propose a panel including themselves, other IP providers, and IP users to discuss the process of choosing what IP to use in an SoC or FPGA. Target audience is SoC designers and systems companies that would purchase IP and incorporate it into their products.
2. IP Ecosystem (IPE): Providers of tools and/or methodologies designed to help the producers and users of IP perform their tasks more efficiently are invited to propose a panel including themselves and other providers to discuss the design and implementation concerns that IP producers and users should consider as a part of their design process. Target audience is SoC designers and systems companies that would purchase IP and incorporate it into their products.
3. IP User (IPU): Users of IP cores are invited to present slides or a poster describing their experiences incorporating IP into their design, challenges encountered, and the way those challenges were overcome. Target audience is other SoC designers who would like to understand an experienced user’s process and learn from it.
The submission site is now open. The deadline for IP Track and Designer Track submissions is January 20, 2015. For additional submission information and deadlines, please visit http://www.dac.com.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems and for electronic design automation (EDA) and silicon solutions. Since 1964, a diverse worldwide community of many thousands of professionals has attended DAC. They include system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, and methodologies and technologies. A highlight of DAC is its exhibition and suite area featuring leading and emerging EDA, silicon, intellectual property (IP) automotive, security and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (ACM SIGDA).
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Michelle Clancy, 1-303-530-4334