Offering Best Application Density, Scalability and Power Efficiency for Data-Center and Carrier NetworksYOKNEAM, Israel, February 23, 2015 — (PRNewswire) —
Introducing the TILE-Mx, a new family of multicore processors featuring an unmatched combination of high-performance processing, throughput and efficiency:
- One hundred64bit ARM CPU cores in one chip for highest compute power
- Mesh cores interconnectivity for massive bandwidth, low latency and linear scalability
- Multitude of networking hardware accelerators for high-performance data-path packet processing
- 200-Gigabit throughput for unmatched application performance and systems' high port count
- Best power/performance ratio for small systems' rack and power footprint
- Standard ARM ecosystem for leveraging software from the open source community and for easy software portability between platforms
- Empowering networking applications including load balancing, security, network monitoring, NFV & SDN, virtualization, IDS/IPS (Intrusion Detection/Prevention), application recognition and video processing
- Target markets versatility including data center, cloud, enterprise and carrier networks serviced by network appliances, white boxes, NFV servers and application software vendors
EZchip Semiconductor Ltd. (NASDAQ: EZCH), a leader in high-performance data-path processing solutions, today unveiled the TILE-Mx multicore processor family that incorporates an unprecedented one hundred ARMv8-A 64-bit cores, and is specifically targeted for high-performance network applications and network functions virtualization (NFV). A unique combination of the highest ARM core-count, a highly efficient mesh for linear scaling of the interconnected cores, and powerful market-proven accelerators for packet processing, provide for radical new multicore processors tailored to the new network architectures that are evolving towards open hardware platforms, software virtualization and rising traffic loads. The TILE-Mx marks EZchip's major thrust into the multicore market with a highly differentiated product line following the Tilera acquisition completed last November. EZchip will present details of the TILE-Mx at the Linley Data Center Conference on February 25, 2015 in San Jose, California.
Multicore CPUs represent a fast growing market - 38% growth from 2012 to 2013 according to the Linley Group 2014 Guide to Multicore Processors - and are used in a wide variety of systems, particularly in network appliances, white boxes, server blades and NFV servers to perform load balancing, security, network monitoring, SDN & NFV, virtualization, application recognition and video processing for data center, cloud, enterprise and carrier networks.
Increasing traffic loads and rising packet processing complexity are putting pressure on available multicore CPUs for more compute power, higher throughput, and greater power efficiency. EZchip's TILE-Mx is specifically designed to address these challenges through a highly parallel and optimized architecture leveraging proven hardware accelerators from EZchip's market leading network processors, and Tilera's many-core processors with market leading performance-per-watt and linear scaling. Furthermore, the TILE-Mx is built around the ARMv8-A 64-bit ARM Cortex®-A53 cores, ensuring standard processor architecture, with great power efficiency and a large and open software ecosystem readily available for application developers. The result is a powerful and efficient multicore processor, optimized for data-path throughput and combining high performance management and control-plane processing.
Central to the TILE-Mx is the integration of an unprecedented 100 ARMv8-A 64-bit CPU cores into a single chip. Through a unique mesh architecture with coherent cache and massive bandwidth that provides linear scaling of application performance, the TILE-Mx provides huge compute power for any data center workload. In order to optimize applications' data-path packet processing, the TILE-Mx also incorporates EZchip's market-proven hardware-based accelerators including the industry's leading traffic manager featuring 256K queues with traffic shaping, policing and SLA (Service Level Agreements) enforcement, hardware accelerated packet classification and table lookups for millions of flows, statistics updating for millions of counters, pattern matching, cryptography and public-key acceleration. In addition, the chip boasts an optimized memory architecture with extremely high bandwidth to both the internal and external memories, and numerous interfaces for 1GE, 10GbE, 25GbE, 40GbE, 50GbE and 100-Gigabit Ethernet as well as PCI-Express. For maximum software simplicity and platform flexibility the TILE-Mx supports the ARM ecosystem including industry standard hypervisors for virtualization, the Linux® operating system, software development toolset, DPDK libraries and drivers for fast packet processing, ODP application programming interfaces, as well as open source and third party software stacks for OVS (Open Virtual Switch), routing, IPsec, SSL, load balancing, IDS/IPS (Intrusion Detection/Prevention) and application recognition.
For NFV and SDN (Software Defined Networking) the TILE-Mx empowers a variety of solutions to offload and accelerate deployments, bringing higher performance and higher applications density, with fewer servers and VMs (Virtual Machines) to manage. The TILE-Mx solutions for NFV and SDN enable platforms such as appliances, blades, intelligent adapters or NFV servers to be optimized for running VNFs (Virtualized Networking Functions), ultimately increasing the throughput and scale, and reducing the power and cost of NFV and SDN deployments.
"We are bringing to the market a new type of highly differentiated multicore processor, leveraging the best from EZchip's and Tilera's technologies, and specifically architected to address the next generation of high-performance data center, cloud and carrier networks," said Eli Fruchter, CEO of EZchip. "The combination of EZchip's and Tilera's market-proven leading technologies enables us to develop a new multicore processors family that uniquely integrate powerful networking capabilities together with the highest number of processor cores to address a wide range of applications and market segments. While our NPU portfolio and, in particular, the new NPS is the highest performance merchant NPU, we expect the TILE-Mx to be the highest performance multicore CPU. As we have accomplished in the NPU market, we believe that through the strongly differentiated technology that we are now developing we will dramatically increase our share in the multicore market in coming years and become a leader in the multicore CPU market."
"We see strong demand for 'optimized-for-purpose' platforms that combine server-class compute with differentiated IO, networking and storage capabilities across a range of infrastructure applications," said Ian Ferguson, vice president, segment marketing, ARM. "EZChip's use of dense clusters of highly efficient ARM processors on a single chip enables an extremely efficient platform for virtualized, high performance applications with improved total cost of ownership (TCO). The ARM partnership is rapidly delivering new and exciting technology that will address the future requirements of intelligent, flexible infrastructure."
"With its vast complex of 100 Cortex-A53 cores, EZchip's TILE-Mx100 raises the bar for 64-bit ARM processors," said Tom R. Halfhill, senior analyst for The Linley Group. "It's also a hybrid design that combines the ARMv8 cores with EZchip's packet-processing accelerators and the on-chip scalable mesh acquired with Tilera last year. This fully programmable chip can run open-source operating systems, hypervisors, and other software for high-performance networking and communications."
"Qosmos leads the market for embedded Deep Packet Inspection (DPI) for SDN and NFV," said Erik Larsson, Vice President of Marketing at Qosmos. "By combining Qosmos with EZchip, our joint customers can implement new network architectures combining deep network intelligence with very high bandwidth."
The TILE-Mx is scheduled to sample in the second half of 2016. In order to address multiple performance, power and cost points, EZchip will offer a complete portfolio of processors with the TILE-Mx architecture including smaller versions of the chip with 64 and 36 ARM cores. EZchip will present details of the TILE-Mx at the Linley Data Center Conference on February 25, 2015 in San Jose, California.
EZchip is a fabless semiconductor company that provides high-performance data-path processing solutions for a wide range of applications for carrier, cloud and data center networks. EZchip's broad portfolio of solutions includes network processors, multicore processors, intelligent network adapters and high-performance appliances with a comprehensive software ecosystem, which scale to terabit performance levels. EZchip's processing solutions excel at providing high performance and exceptional flexibility coupled with superior integration and power efficiency. For more information on our company, visit the web site at http://www.ezchip.com.
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Forward-looking statements are statements that are not historical facts and may include financial projections and estimates and their underlying assumptions, statements regarding plans, objectives and expectations with respect to future operations, products and services, and statements regarding future performance. These statements are only predictions based on EZchip's current expectations and projections about future events based on its current knowledge. There are important factors that could cause EZchip's actual results, level of activity, performance or achievements to differ materially from the results, level of activity, performance or achievements expressed or implied by the forward-looking statements. Those factors include, but are not limited to, the impact of general economic conditions, competitive products (including in-house customer developed products), product demand and market acceptance risks, customer order cancellations, reliance on key strategic alliances, fluctuations in operating results, delays in development of highly-complex products, the consummation of the Tilera acquisition and other factors indicated in EZchip's filings with the Securities and Exchange Commission (SEC). For more details, refer to EZchip's SEC filings and the amendments thereto, including its Annual Report on Form 20-F filed on March 27, 2014 and its Current Reports on Form 6-K. EZchip undertakes no obligation to update forward-looking statements to reflect subsequent occurring events or circumstances, or to changes in our expectations, except as may be required by law.
EZchip IR Contact:
Jeffrey A Schreiner, Director, Investor Relations
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SOURCE EZchip Semiconductor Ltd
|EZchip Semiconductor Ltd