The free riscvOVPsim updates are available now on GitHub.
Imperas will demonstrate the new Vector and Bit Manipulation extensions as well as other RISC-V models and virtual platforms, at the upcoming RISC-V Workshop in Zurich Switzerland next week.
The riscvOVPsim solution is an entry ramp for development, as well as a compliance testing tool. For developers of more advanced RISC-V designs, who need multi-core support and advanced debug, verification and analysis tools, Imperas also offers full-capability virtual platforms of some leading RISC-V platforms including the multi-core SiFive U540 and many others. Further details are available at www.imperas.com/riscv.
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
About the RISC-V Foundation
For more information about RISC-V (pronounced “risk-five”), please see https://riscv.org.
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