MIPS selects Imperas Reference Models for RISC-V Processor Verification


“RISC-V is at the forefront of a hardware design renaissance in optimized processors,” said Itai Yarom, VP of Sales and Marketing at MIPS, Inc. “But, an ISA only provides the envelope of possibilities. The art and science of processor optimization requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.”

“The Imperas simulation technology has two unique attributes, it models processors with the accuracy, control, and visibility required for functional DV and secondly, it can be integrated into all the main EDA verification environments.” said Simon Davidmann, CEO at Imperas Software Ltd. “Integrating our RISC-V reference models into a SystemVerilog UVM testbench supports the latest techniques for asynchronous events with ‘step-and-compare’, and provides a single environment to efficiently resolve issues. With this expanded partnership, we are thrilled to support the MIPS strategy for RISC-V.”

At CDNLive in Munich, Germany, May 6-8 2019, Intel Mobileye presented a technical paper, “Hybrid Virtual + Emulation SoC Platform for SW-Drivers Validation”, which highlighted the full Linux OS boot in 32 seconds instead of 2-3 hours on the non-hybrid emulation. This was followed by the Imperas presentation discussing hybrid emulation with Imperas reference models and Cadence Palladium for a MIPS-based SoC. These presentations (SVG02, SVG03) are available for download, with free Cadence registration, at this link.

In 2018, the announcement of the MIPS I7200 multi-threaded multicore processor included highlights from MediaTek for 5G compute performance and Imperas for simulators, virtual platforms, and debug and analysis solutions that help accelerate software development for multicore and multi-threaded processor configurations. The full release is available at this link.

Availability
The Imperas RISC-V reference models and processor verification IP are available now; more details are available at www.imperas.com/riscv.

The free riscvOVPsimPlus package, including several Architectural Validation test suites and support for instruction coverage analysis, are now available on OVPworld at www.OVPworld.org/riscvOVPsimPlus.

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