Someone once told me that a good journalist goes out to cover a story free of any pre-conceived notions. That's the only way, I was told, that you can really hear what people are saying.
This little story is about the FGPA tools used for design, and I'll admit up front that I broke that rule. I went into this series of interviews with a distinctly pre-conceived set of notions. I expected to learn why the big EDA vendors, with the exception of Mentor, seemed fairly uninterested in an aggressive expansion into the FPGA space.
I expected to hear that the big EDA guys couldn't/wouldn't see that reprogrammable, reconfigurable everything is the thing of the future. I expected to be told that the major vendors are ignoring FPGAs to try and shore up their established customer base, those who are doing more traditional cell-based design. I expected to hear from industry prognosticators that the EDA guys who refused to read the (FPGA) writing on the wall were going to end up losing dominant market position.
As it turns out, however, it's not like that at all - at least from what I heard from various people in the industry. The problem isn't with the EDA vendors at all. It's with the FPGA vendors.
The FPGA guys are giving away the tools for free - or essentially, for free. So, compared to, say, $75,000 or $175,000 for a traditional EDA tool, an FPGA tool from an FPGA vendor is only costing you $1,500 or $2,000. A complete flow will run you as little as $2,500. In other words, the tools are essentially free.
And, it's not like the EDA guys are at liberty to say to potential customers, “Watch out, because you only get what you pay for.”
Because the “free” design tools from the FPGA guys are apparently excellent, well designed, and well supported. The EDA vendors can't compete. And, for now, they're not going to try. At least, that's my conclusion. This week, we'll hear from a variety of people - none of whom are FPGA vendors. Next week, we'll hear from the FPGA vendors themselves, and from the leader in the FPGA synthesis market. After you've read it all, you can draw your own conclusions.
So, let's get a quick start out of the gate with a comment from industry oracle, Gary Smith.
Gary Smith, Chief EDA Analyst at Datequest/GartnerGroup - “The FPGA market is a dumb market to be in for any EDA vendor. Because the minute you mention FPGAs [to a potential customer], the price you can ask for the tool goes down by a factor of 10.”
“Right now, the FPGA vendors have really fouled things, as far as the tools are concerned. If they would just quit giving away the tools - something they should have stopped doing in about 1995 - they would have help from the major EDA vendors to support large designs. The ASIC vendors figured that out in the mid-80s. [It remains to be seen], when the FPGA vendors will figure it out.”
Ping Chao, Executive Vice President and General Manager at Cadence Design Systems, Inc. - “The FPGA segment obviously is getting a lot of attention these days. But, it's always a challenge for the EDA industry to figure out how to make money out of it. Strictly speaking, we're not participating in the market. We're continuing to [concentrate] on ASIC and SoC-type design.”
“We do participate somewhat in the FPGA verification market, but we don't have offerings on the synthesis side. We work with Xilinx and partner with them, and that's the extent of our participation in the market at this time.”
“There's at least one angle, however, where we do have an advantage. That's in the structured ASIC market. Recently, we've been working with NEC and other people in that area, but it's not really the FPGA space. It's the gate-array space. So there may be some strategic investments there, but mainly we're just watching the market for the moment.”
Jeff Jussel, Vice President of Marketing at Celoxica Ltd. - “We're sponsoring a Tuesday afternoon panel at DATE on exactly this topic - should FPGAs be the focus for EDA tools? We set up the topic based on a survey we did in the last couple of months of 2003. We found from that survey that the number of FPGA design starts are now about three times the number of ASIC starts, from 1800 design starts last year, to 2700 this year - a 50 percent increase.”
“We asked a bunch of designers about the role of ASICs versus FPGAs. Our argument said, if design starts are all going to FPGAs, per data from Gartner and our own data, and EDA tools traditionally follow the design starts because that's where you're selling seats, and if EDA makes money on those design starts, then shouldn't EDA be spending more money on FPGAs?”
“The topic may not be as sexy as talking about deep submicron, or the effects of 90-nanometer, or timing closure, but we still ask - if that's where the design starts are, isn't that where the EDA focus should be? The DATE panel will address increasing the functionality and decreasing time to market for FPGAs.”
“At Celoxica, we're focused on system-level design for FPGAs. Our tools allow a C-based design to be compiled directly to an FPGA. In that regard, we see a couple of things. The solution we provide is a unique flow for customers of FPGA vendors. Customers who need to get to system FPGAs need these kind of system-level design tools. For customers who might not get into hardware design, we provide a path for them to implement their design in an FPGA.”
“Typical markets might include data security, for example, where complex algorithms are needed to get to gates. If the customer doesn't want to go through gates, they can use our tools. In addition, we ourselves are a customer of the FPGA vendors, because we sell FPGAs on our boards.”
“Clearly, the FPGA vendors are important partners for us - and investors as well. They sell silicon, not software tools. No one at Altera or Xilinx is going to make money on tools. But traditionally, they've had to provide the tools because the [third-party] vendors just weren't there. When the FPGA vendors first started, there were only RTL tools available. The only way [the FPGA vendors were going to succeed] was to develop their own tools because EDA wasn't supporting FPGAs. Now that we're getting into the system space, the FPGA vendors need to get on with [partnering] with third-party vendors.”
“[From the perspective of the EDA vendors], I think we'll continue to see the traditionalists saying, 'No, we need to continue to focus on ASICs.' In fact, that's because we're all semiconductor guys and we're very used to the market being a certain way. But, if this thing is truly what's happening and we're moving to another level above the silicon, then it does change the game. I can't fault Mentor [for their commitment to FPGAs], but even their focus has been on the traditional side with simulation and synthesis, not on the system side.”
“The FPGA vendors have had a vested interest from the beginning in having a viable RTL flow in-house. The system-level space, however, presents a new area that they're attacking by partnering with third-party vendors. The FPGA vendors actually provide an important channel for us in that their customers are the people we're trying to reach, as well. They also help us out as technology partners. In fact, Xilinx is an investor in Celoxica. They ship our tools.”
“Relationships are very important [in all of this]. Both Xilinx and Altera are important to us - we put all of their products on our boards. As EDA vendors, we need to [protect and promote] these relationships as they are critical for our success.”
“Right now, Xilinx and Altera are taking over the commodity part of the FPGA business. At the high end, it's IBM where they've got a monopoly - highest performance, highest volume. They're the ones who can afford to put out millions of dollars for the newest fabs. In the middle, you've got people who can't afford the high-end, but who also can't compete with Xilinx and Altera.”
“Also what we're finding is that the design platform - an overused term - with a processor, maybe a DSP, maybe some customer hard IP, plus some blocks of reconfigurable logic, is being used to create a design for a particular niche. It's the hard IP and reconfigurable logic, which allows them to differentiate their product. Those are the people looking for system-level design tools that target the problem. So, that's what we're seeing, a [set of] mid-level customers attacking various market niches by way of application specific reconfigurable something-or-other. As an industry, we'll have to come up with a term for this device eventually. But for now, there really isn't a consistent term being used here.”
“[Bottom line] - as ASIC NREs go through the roof, you're looking at $2 million to $3 million for NREs, plus engineering time, plus tools, plus a complex design flow for an ASIC. And because it's deep submicron today, the chances of a re-spin are very high. So, you're looking at $20 million to get an ASIC out the door. It's reaching the point that, if the performance is good enough an on FPGA, it's probably cheaper in the long run to go with the FPGA and stay with the FPGA [through the lifetime of the product].”
Sherry Hess, Vice President of Marketing at Ansoft Corp. - “Currently, Xilinx is endorsing us as an EDA vendor. They're recommending to their customers that after they get their product from silicon, that they use Ansoft tools to get maximum performance when the Xilinx product goes onto the board. Xilinx is a customer of ours as well, because the Xilinx field organization is a bit of a consulting organization - even on some of their test boards, they're using Ansoft tools. So, although we're somewhat outside of the discussion, Xilinx is important to us, both for their endorsement to their customers and as a customer of ours.”
Dino Caporossi, Vice President of Sales at Hier Design - “FPGAs have become a reality gradually over the past 3 years, due more or less to the increasing cost of the ASIC and the decreasing cost of the FPGA. The crossover point today is around 50,000 units. It's more difficult to justify the first-run huge expenditures of an ASIC without knowing what the market is. You can try out the market first in an FPGA, and then you can reduce the cost of the product by going to an ASIC.”
“We've done some studies and have called around to find out if ASIC starts are down and FPGA starts are up. When we go and visit accounts that used to be very heavily ASIC, some of those accounts have actually flipped entirely the other way and are almost entirely FPGA today.”
“The reason that Hier Design was put into place is because we wanted to exploit the fact that the tools haven't kept up with the complexity of FPGA design. FPGA vendors have their gate counts and ASIC guys have theirs. The equivalent of 250,000 ASIC gates is about 1 to 2 million system gates. They're slightly different metrics, but in either case, when you get to that complexity level, you need to look seriously at getting better tools.”
“The market for FPGA design tools is still predominantly the communication market, although we're seeing a large spectrum of users. Cisco uses a ton of FPGAs in their products, and there are big budgets in homeland security, things like airport scanners - things that are stationary and not power sensitive are good applications for field-upgradable products. If terrorists change their payload, for instance, the software can be quickly downloaded and the product altered to match the updated need. Also in defense, the military has taken some dumb bombs and made them smarter using the flexibility on FPGAs.”
“Xilinx is an investor in Hier and is also using our tools. In some cases, we've even worked closely with Xilinx FAEs to provide solutions to customers' tough design problems. We're helping to unstick those problems for the customers. To some extent, we're improving on what they've got. FPGA vendors have a vested interest in putting out the best tools, but they're not always able to come up with the leading-edge solutions.”
“It's kind of the same thing that happened 15 or 20 years ago in the ASIC world. The ASIC guys decided that the chips were just so complex, and that the design software needed to be so complex, that it didn't make sense for them to do their own tools in-house anymore. At some point, the EDA vendors came along and said they could do the tools better and the ASIC guys could then focus on their core business. Now it's the FPGA vendors who are realizing that the EDA industry can focus on the tools, while they focus on their core business.”
“We're offering tools for the hierarchical design and analysis of FPGAs - something that's beyond floorplanning, which bring block-based methodologies to FPGAs. This tool functionality did not exist before. If you needed to do a design change, you had to do it in a flattened netlist. Now all you need to do is to correct a single block. We're trying to attack the toughest problems at Hier. I believe we're on the leading edge of FPGA design. When we formed this company, we asked who has been a success in this area and what did they do correctly. None of the people who had tried to do physical synthesis at the RTL level were successful. We saw that Magma and Silicon Perspectives were able to
achieve these goals by doing this type of thing at the back end. So we choose to mimic their ASIC formula for success. “
“Right now, Cadence is hedging their bets by investing in us - they're a major investor in Hier Design. We started fresh and have developed tools that look at the design from the front end, not from the back end after things have started to break down.”
“The design world is changing. There are major accounts today where the ASIC designers are now in the FPGA world. They get into that world and say, “Wait, where are the tools like the ones we had in the ASIC world?' The difference between the ASIC and the FPGA is in the flexibility. ASIC designers can mess with the routing and move things around, but the routing is a black-box [process] on the FPGA. There's room for artistry there, but it's a different process than in ASIC design.”
“We believe there are about 85,000 design starts world wide on FPGAs, versus 3,000 starts for ASICs, which is another factor. You need our tools when you're getting to the point that more than one designer has to design something. With multi-million FPGAs, you need team work and you need hierarchical design.”
“Clearly FPGA customers are not accustomed to paying for tools, but as we prove the value of our tools, we're seeing much quicker sales. In the FPGA world, it's true that our tools are relatively expensive compared to the free tools from the FPGA vendors. But if we save weeks or months on the project, the ROI is obvious.”
Industry News - Tools and IP
Atrenta Inc. announced that Toshiba Corp. Semiconductor Co has selected Atrenta's SpyGlass Predictive Analyzer to “enforce design reuse and excellence initiatives early at RTL and thereby ensure high RTL productivity. SpyGlass' unique predictive analysis technique enables Toshiba engineers to perform detailed structural analysis at RTL and identify complex issues such as clock domain crossings, synchronization, connectivity checks, clock/reset requirements and Toshiba Design for Test guidelines early in the design cycle. Toshiba is further standardizing on SpyGlass and creating Toshiba-specific rules for internal use.”
Legend Design Technology, Inc. announced the company's MSIM circuit simulator now provides full modeling support of BSIM4.3.0 for nanometer process technology, and that “MSIM with the new BSIM4.3.0 model has been successfully used for simulating state-of-the-art 90-nanometer CMOS memory designs by major foundry customers. It has been observed that the MSIM simulation results show there is approximately a 3-percent difference when considering stress effects (SA, SB) while measuring rise and fall times. For BSIM4.3.0 support, MSIM has been built to handle the additional electrical mechanisms, model parameters and equations associated with the new model.”
Those additional functionalities include: a new scalable stress effect model for process induced stress, a unified current-saturation model, a new temperature model format, enhanced accuracy and flexibility of holistic thermal noise model, improved accuracy of forward body bias model, and an extension of gate direct tunneling model to multiple-layer gate dielectrics.
Mentor Graphics Corp. announced the availability of ADVance MS (ADMS) version 4.0, which now includes support for SystemVerilog and SystemC languages. The company says that ADMS 4.0 also contains expanded tool capabilities that will allow designers to verify that designs are functioning to the original specification in either a digital-centric or analog-centric design flow. ADMS version 4.0 now delivers full language support for SystemVerilog, SystemC VHDL, Verilog, SPICE, VHDL-AMS, Verilog-AMS and C. Mentor says that, with ADMS 4.0, it is now “delivering a single common platform to extend both digital verification and analog verification for mixed-signal designs.”
SofTech, Inc. and Cimmetry Systems announced a partnership. SofTech is licensing Cimmetry's AutoVue visualization and collaboration technology for its ProductCenter PLM (product lifecycle management) solution. The companies say, “Integration of AutoVue technology with ProductCenter PLM will extend the collaboration capabilities of ProductCenter, enhancing the solution's document management, design integration, configuration control, change management, and enterprise integration capabilities for optimizing product development.”
Synopsys, Inc. announced that the new release of PrimeTime has “set a new performance standard for static timing analysis and sign-off of 90-nanometer designs, enabling timing analysis of 100-million gate designs. Customer benchmarks show an average of 3x runtime improvement and up to a 3x data capacity improvement over the previous release.” Synopsys says the improvements are due to algorithmic improvements in reporting and static timing analysis, combined with a new save-and-restore capability that enables concurrent timing analysis of large, complex designs.
Also from Synopsys - The company, in conjunction with TSMC, announced that TSMC's libraries will now be distributed through Synopsys' DesignWare Library. The companies say, “the collaboration provides the more than 25,000 DesignWare Library users, at no additional cost, access to standard cell and I/O libraries created by TSMC and optimized for the company's 0.15-, 0.13-micron and 90-nanometer Nexsys Technology for SoC foundry processes. Synopsys will also offer TSMC's memory libraries for an additional fee. This agreement is the latest collaboration in a long-term relationship between the two companies. The agreement provides that both companies will optimize TSMC's standard
cell and I/O libraries and produce design flows that deliver higher productivity and design quality to users.”
Following the announcement, I spoke by phone with Phil Dworsky, Director of Marketing for DesignWare IP at Synopsys. He said, “This is certainly a collaboration between two leaders acting on our customers' drive to bring more IP to them through a trusted IP channel, the DesignWare library. Our aim is to jointly lower our customers' risk and increase their time to volume. The process involves creating and validating flows, together with the silicon library and process, and will deliver standard cells and I/O libraries to our customers free of charge. We're going to give away the TSMC library, not that we won't make money in the equation. In fact, everybody stands to benefit and the [strategy] is well within our business model.”
I also spoke on the same phone call with Andrew Moore, Deputy Director of Service Product Marketing at TSMC. He told me, “We've worked together for a year. Our hand-off from designers is GDS. Now they will have a full set of tools to check that layout. More recently, we've been working with Synopsys on the TSMC reference flow, which includes most of the tools in the Synopsys platform. We've been making these libraries all along. Now we're giving them to Synopsys and asking them to give us any 'gotchas' back. This announcement with Synopsys cements our technical and business relationships with the company.”
Target Compiler Technologies NV announced that its Chess/Checkers retargetable tool-flow has enabled Gennum Corp. to accelerate the design of its newly developed 'Yukon' ultra low power microprocessor core, optimized for use in hearing instrument products. The Yukon core is the embedded controller used in an audio processing system already shipping in volume. Gennum says it used the Chess/Checkers tool-suite to develop a new, highly optimized application specific DSP core as a key component of a new multi-processor open platform. The new processor is currently made available to Gennum's customers on an FPGA prototyping board and will be in production later this year.
Don Shaver, Director of Product Development at Gennum, is quoted: “We wanted to design the best-in-class performance microprocessor and DSP cores for our specific type of application. Our aggressive schedules required us to perform simultaneous validation of the hardware and our application software. The maturity of Target's retargetable C compilation technology and the automated path to hardware generation that they offer were compelling reasons to select the Chess/Checkers tool-suite.”
Compiler Technologies was a spin-off from IMEC in 1996 and supplies retargetable tool suites for designing and programming flexible IP cores.
TransEDA and Verisity Ltd. jointly announced the availability of a flow in which TransEDA's Reqtify specification coverage technology is interfaced to Verisity's vManager verification management solution, linking design specification requirements to verification. The companies say the link between Reqtify and vManager brings the same best practices used by engineers in the automobile, aeronautics and defense industries to the semiconductor industry.
Per the Press Release: “Development teams need to ensure that all specification requirements have been verified in the final design. With today's systems becoming more complex, the need for requirements traceability and impact analysis during the design phase becomes crucial in order to enable quality development in SoC design. The interface between TransEDA's Reqtify and Verisity's vManager allows designers to boost the quality and time-to-market of SoC designs. Designers can verify that the design meets the initial specifications and replies to the needs of the customers.”
TSMC and Cadence Design Systems, Inc. announced efforts to create an integrated design capability that accelerates customers' time-to-volume for nanometer design. The companies say that as a result, Cadence becomes the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries, and memories. In addition, the two companies announced they will collaborate to integrate TSMC's 0.15-micron, 0.13-micron and Nexsys 90-nanometer standard cell, I/O libraries and memories with the Cadence Encounter design flow, which was qualified to be included as part of the TSMC Reference Flow. The companies also say these developments are supported by the Cadence Design
Foundry design services organization as well, which is a member of TSMC's Design Service Alliance.
Verific Design Automation announced that its products now support Accellera's property specification language (PSL)/Sugar - all of its HDL component software packages now include a PSL/Sugar reader and will, therefore, enable assertion-based verification. Additionally, Verific announced it has joined the PSL/Sugar Consortium. Harry Foster, the consortium's formal verification technical committee chair, is quoted: “The PSL/Sugar Consortium is pleased that Verific is offering assertion-based specifications within its HDL component software packages. This allows EDA companies to swiftly introduce native PSL/Sugar support in their verification tools. We were waiting for something like this to happen.”
Coming soon to a theater near you
DVCon 2004 - Organizers have announced the title for the keynote address due to be delivered by Cadence President and CEO Ray Bingham. The title of his talk is, "Making Design and Verification a Strategic Business Asset." The talk is set to showcase Bingham's vision for “taking the industry to the next level by providing valuable insight into the important role business transformation plays in the development and proliferation of technology and new products.” Right now, I don't really know what a business transformation is, but I hope to learn more at the talk.
2004 GSPx - The 2004 Global Signal Processing Expo and Conference, an embedded signal processing event, will take place from September 27th to the 30th at the Santa Clara Convention Center. Per the organizers, “GSPx provides opportunities for design engineers and developers to share their knowledge with an international audience of thousands of engineering colleagues. The expo brings together large companies from all over the world and is an opportunity to see, first-hand, the latest developments in state-of-the-art solutions, including design methodologies and
processes, test and verification tools, and embedded applications. The expo keeps developers, engineers, designers, project managers, and executives abreast of recent advances and future demands.” The conference is co-sponsored by OCP-IP, Accellera, the Embedded Linux Consortium, SystemC, and the Rapid I/O Trade Association.
EDAA Lifetime Achievement Award - The European Design and Automation Association announced that the winner of this year's EDAA lifetime achievement award is Prof. Hugo de Man. Prof. De Man works at the Catholic University of Leuven, Belgium. He also worked at the Interuniversitair Micro-Electronica Centrum (IMEC) in the same city, where he was one of the Vice-Presidents.
The award will be presented on February 17th during the keynote session at DATE 2004. EDAA says its decision reflects De Man's scientific achievements as well as his impact in industry. His many scientific achievements include the modeling of semiconductors, the design of analog, mixed-mode and digital simulators, research on the specification, verification and synthesis of telecommunication-oriented system design, contributions towards the design of asynchronous circuits, and novel system-level optimization techniques.
Per the Press Release: “Prof. De Man successfully combined his work on design automation with that on the actual design of electronic circuits. Some of the circuits that he helped to design have been in use for over a decade. His research led to the publication of 152 international journal papers and 438 internationally refereed conference papers. He supervised 37 PhD dissertations and won eight best paper awards and one best circuit award. Based on the research that he guided and motivated by his entrepreneurial
spirit, several companies have been founded in the field of design automation (CoWare, Target Compiler Technologies, Adelante Technologies - now ARM Belgium, PowerEscape), design services (Ansem, Easics - now a Transwitch company) and applications (Sirius - now Agilent Belgium, Acunia, Septentrio). He is one of the most influential scientists in design automation in the world.”
The Structured ASIC Association (SAA) - Per the Press Release: “A group of Structured ASIC manufacturers and EDA companies, including Chip Express, Lightspeed, Synplicity, and Tera Systems, announced that they have formed the Structured ASIC Association (SAA). The founding members are collaborating to firmly establish structured ASICs as a unique market segment and educate the industry about this new technology.”
“As defined by the SAA, Structured ASICs are a new category of semiconductors targeted at customers who are looking for the fast-turn capabilities of FPGAs without their high unit cost, and those who want to take advantage of the relatively low unit costs of ASICs without paying high NREs. Structured ASIC devices reduce much of the up-front NRE and shorten development time by using pre-diffused base metal layers to implement logic cells, memory and I/O common to many designs. Custom logic for a specific application is then implemented in the final few layers of metal, requiring far fewer mask layers for each design.”
“Customers using Structured ASICs reap many of the performance and cost advantages of a full custom ASIC in a device which can be fabricated in as little as three weeks. Using this revolutionary new technology, design teams can build complex ASICs for 25 percent or less of the development cost of a standard cell device, at a unit cost approximately 90 percent less than a complex FPGA.”
Atrenta Inc. announced that its SpyGlass Constraints product, a design constraints validation solution, has been selected as a finalist for this year's EDN Magazine Innovation of the Year Award. This program is dedicated to honoring outstanding engineering products in the electronics industry. A panel of EDN's technical editors selected SpyGlass Constraints in the EDA Design Exploration category.
InTime Software Inc. announced that its InTime's Time Director RTL Timing Analysis (RTA) and RTL floorplanning software has been selected as a finalist, as well, for this year's EDN Magazine Innovation of the Year Awards, as one of four finalists in the EDA design exploration category. The program honors outstanding products, ranging from integrated circuits to test equipment, as well as the creative engineers who invent them.
TDA Systems announced that it, too, has been selected as a finalist for this year's EDN Magazine Innovator/Innovation Awards. TDA Systems says its IConnect MeasureXtractor automated model extraction tool was selected in the EDA - Physical Analysis category. The Innovator of the Year Award honors an engineer, engineering manager, or team of engineering professionals currently working in the electronics industry. Nominees must have demonstrated innovation that resulted in a significant advance in technology and/or product development during the past 12 months.
Atrenta Inc. announced that it has partnered with Transfer Nederland BV to deliver Atrenta's SpyGlass predictive analysis products to the BeNeLux region. The companies say that this new distribution relationship further extends Atrenta's presence in Europe, which already includes a distribution network in the U.K., Ireland, Israel, Germany, Austria, and Switzerland, and direct sales efforts in France and the U.K.
Cadence Design Systems, Inc. announced that Lip-Bu Tan, Chairman and Founder of Walden International, has been elected to the Cadence Board of Directors. Per the Press Release: “Lip-Bu Tan has been active in the venture capital industry for the past two decades with a special focus on software, semiconductors, and communications. He introduced and pioneered the U.S. venture capital concept in Asia and contributed towards the promotion of early-stage technology investing in the Asia-Pacific region. He is a board member of Flextronics, the National Venture Capital Association, a member of the Visiting Committee for the Department of EECS at MIT, and a member of the Committee of 100.”
Tan has an MS in Nuclear Engineering from MIT, an MBA from the University of San Francisco, and a BS from Nanyang University in Singapore.
CriticalBlue has added venture capitalist Lucio Lanza to its Board of Directors. Lanza is Managing Director of Lanza techVentures, which recently invested in the company's $2 million round investment. Before founding Lanza techVentures, Lanza was general partner in U.S. Venture Partners, chief strategist and leader of merger and acquisition activity for Cadence Design Systems, and held executive management positions with several companies including Olivetti, Intel, Daisy Systems, and EDA Systems.
Hier Design Inc. announced that it has opened a regional office in Andover, MA. Vice President of Sales Craig Robbins will work from the new office, as will the regional account manager and several AEs.
Magma Design Automation, Inc. announced its expanded users group, MUSIC, will host a series of meetings in India, the U.S., and the U.K., starting with a conference in Bangalore in August. MUSIC stands for "Magma Users Summit on Integrated Circuits." The company says the former name, “Fusion,” was too closely tied with just one of Magma's tools. The new moniker is intended to represent Magma's “broader portfolio.”
Tharas Systems, Inc. announced that Gary Kiaski has joined the company in the capacity of Worldwide Sales Vice President. Kiaski has 20+ years of experience in domestic and international sales in EDA and most recently was VP of North American sales for Axis Systems. Previously, he served in an executive capacity at Innoveda, where he was responsible for sales staffs through three mergers and a spin off from Synopsys in 1998. Prior to Innoveda, he held various sales management positions at Calay and Intel.
Verisity Ltd. announced it has completed its acquisition of Axis Systems, Inc., a privately held company that offers simulation technology for hardware, embedded software, and system-level verification. The announcement of the definitive agreement to acquire Axis was made last December. Axis' President and CEO Mike Tsai will be Executive Vice President at Verisity and General Manager of the Platform Division. Steve Wang of Axis will serve as Vice President and Integration Executive at Verisity.
Per Gary Smith, at Dataquest GartnerGroup: “The acquisition puts Verisity in a position to become the leading power in ESL verification. Without the purchase, they would have had a hard time fighting off SystemC in the language wars. Now, they don't really have to. Now they will need to buy whoever is important in the design space, but we don't know who that is just yet. The leader is CoWare, but it's still early. We don't expect that market to be solidified until 2006. So, stay tuned.”
X-FAB Semiconductor Foundries announced it has increased its sales presence and technical support in the U.S., and added distributors in the Asia Pacific market. The company recently opened a new sales office in Boston, MA. Tom Riedl will head up that office. In addition, X-FAB has hired Aaron Pollock to handle sales for the company's Silicon Valley office. Per the press release: “Both professionals bring extensive foundry experience gained from corporate positions at TSMC and Dongbu.”
Bits & Bytes
1 - ChipVision Design Systems AG
ChipVision is based in Oldenburg, Germany. It was 5:00 PM their time, 8:00 AM my time when we spoke by phone on February 11th. The conversation included Joachim Riewesell, Chief Marketing Officer for the company, and Dr. Laila Kabous, Technical Marketing Manager. It's always interesting to hear things from the European perspective, so I enjoyed hearing their comments.
Riewesell: “It's nice to talk to you. We're just about to go home, as our workday is finishing. We're going to go have some dinner and [laughing] when we're done here, you can go have some breakfast. Both Dr. Kabous and I joined ChipVision two years ago. She and I are doing the chief marketing activities for the company right now.”
Kabous: “We received our initial funding last year just before DAC. But there were 10 years of research [prior to that], which led to the founding of ChipVision.”
Riewesell: “We started with 5 people a year ago. Now we have 15 people, including numerous engineers and good management. We hope to be at 25 people soon. We started marketing our product last June. We have offices here in Oldenburg, and an office in San Ramon, CA, which is the home of Stan Krolikoski, our CEO. Stan joined us from Cadence. Currently, we have distributors in Asia, Japan, and Taiwan. Through those [relationships], we have connections with the CEOs of many companies with contacts in the Asian business environment.”
“Our tool, ORINOCO, is a system-level power estimation tool. In the very early stages of the design flow, you [have the ability] to have the highest impact on power as that's when you're deciding on the fundamentals of the design. That's why we work at the specification level.”
“Already at the RTL and gate level, there are lots of hot-shot companies out there. But, there are no companies that have what we have. CoWare markets PowerEscape, but that tool focuses on memory. No one else has something in the power area.”
“We take the C code, or the SystemC code, that describes the functionality of the design, and we run this through the compiler. During the compilation, we actually instrument the software code. We add special statements, so that later on, when the software is being executed, these statements are written into a different file. This file and the one created during compilation go into ORINOCO, an annotation takes place, and the tool can then perform the estimation.”
Kabous: “It's like doing a quick synthesis, and then doing a power architecture based on that. The person doing the RTL design than has all the information available to refine the design.”
Riewessel: “When you talk to Gary Smith from Dataquest, he says that those who are able to remain in this space will have a very big future. Here in Germany, Synopsys and Cadence are both shutting down their system-level groups. They don't have anything [coming up] in the drawer for system-level design. I think they're saying, 'Let's put our business units where they can make more money.' [Apparently], they don't think that's in system design in Europe.”
Kabous: “I think what we're saying is that the big boys are pulling out of system-level development, although that may change in the future.”
Reiwessel: “We're seeing DATE as very, very important for us. Many European companies [and customers] come to DATE who don't have the budget to attend DAC. So, it's very important for us to be there.”
2 - Silicon Dimension, Inc.
Don Zereski is President and CEO at Silicon Dimensions. I spoke with him on February 10th. Michael Munsey, Vice President of Marketing, was also in on the call. It was cold where they were sitting on the East Coast. It was sunny here on the West Coast.
Zereski told me, “We're hiding here in a snow bank on the East Coast, just outside of Boston. Nonetheless, it's a very exciting time to be opening a new business. I don't think we could have hit the timing any better for the introduction of the company.”
“We've personally visited some 42 customers and virtually every customer we've seen in 8 weeks, has seen more business than they've seen in the last 2 years - some are so busy they're even asking us to do design work for them. We are doing a little bit of design consulting, but it's not really a long-term part of our business model. We'll do it to help out a customer in a pinch, but it's not really a long-term goal for us at all to be providing services.”
“[Meanwhile], we've been in a stealth mode for quite a while here, developing the product. It went through beta tests last fall, and we'll be releasing product here in 2 weeks. We now have several evaluations underway. We're moving forward with our staffing - mainly hiring sales and FAEs - and we're moving toward real revenue in this quarter.”
“We are seeing very, very positive things for overall business, although we've had difficulty at times having people appropriate the resources for tool evaluation. Once we go through a demo, however, and show them what a tool can do, they're very happy to find resources for that evaluation. In approaching a customer, we have to get to the right people, those who understand the long term benefits of our tool - the logic designers and the managers responsible for the overall project.”
“However, we also go to top management as well. For engineers and managers, it's an improved project schedule, ease of use, and the ability to provide quality netlists to the back-end folks that [they respond to]. For top management, it's ROI and risk management that makes [our offering] attractive. They see that we can cut 4 or 5 months out of the design process by minimizing iterations.”
“Our technology arose from the fact that we're all very frustrated with the existing tools. Our collective team here at Silicon Dimension has done some 300 ASICs combined. Each one of us has sat through various post-mortems on projects and we've seen the same issues come up each time. There's too little floorplanning and analysis being done on the front end. And it's taking too long to get quality [information] to the back-end folks. In other words, there's been little communication between the front-end and back-end folks.”
“Also, the back-end turn around time [was a problem] - the back-end gets the netlist and turns it around back to the logic designers. This process has [traditionally] often been more than just a matter of hours or days, it's often been a matter of weeks. It's created a tremendous problem in terms of the overall schedule. Our team sat down one day and looked at about 150 different elements like these, things that we had observed in our experience, and felt that if we could resolve them, we could provide both the logic designer and the physical designer the ability to avoid false starts.”
“We started with no pre-conceived notions, but with a clear problem set and a clear set of solutions. The Chip2Night platform is a suite of technology modules that directly address problems that the logic designer [must face], and gives him some understanding of the back-end and the issues that the physical designer [must face]. It allows the logic designer to provide the quality netlist that the physical designer needs. Those 3 or 4 months of back-and-forth iterations are now solved.”
“The logic designers care [about these things] because they want their companies to make money. They're responsible for resolving the issues that allow the back-end to produce something that's useful and economically viable. So far, every logic designer we've talked to has been tickled pink. And, from everything we can see, we don't see anybody who's particularly competitive with us. Our tools are designed so that a logic designer can use them effectively after just 2 days of training.”
“[As far as the business climate is concerned], North America is moving forward, but so is Europe. Europe is spending an awful lot of money right now, especially in the area of defense. There's a tremendous amount of spending from the EU into defense, just like here, and there is a tremendous amount of new ASIC starts [associated with that demand].”
“I think the ASIC starts have been dropping over the last couple of years because of risk factors and [the fact that] not a lot of new R&D projects kicked off because of the economic conditions. But now it's changing because of increased spending for homeland defense, electronics, the military area, and consumer electronics. We're seeing very, very positive things for our overall business.”
In the category of ...
Letters to the Editor
Letter No. 1
Please add a table of contents, or headlines, to the top of your articles, so that I can quickly find the specific articles I am interested in. I like your thoroughness and wide range of coverage, but I would rather not have to scan through the articles I am not interested in.
Letter No. 2
I'm sure you've received a thousand messages letting you know that the published URL for the “real” history of the transistor should have been
I think only those who cared enough to find the right link deserved to read the article [EDA Weekly, February 2nd]. Thanks for an interesting read. I hope someday to understand half of it.
Letter No. 3
You might be interested to know The ASIC Group had a great year last year. In response to some discussions with some customers over the past year, we came out with a little tips booklet. We had expected that almost everyone designing chips these days who is still in business would be using most, if not all, industry best practices. To our surprise, we found there are many people out there using “industry worst practices” and this inspired us to do the tips booklet.
The ASIC Group
Letter No. 4
In reference to "But first, a Letter to the Editor" [EDA Weekly, February 9th]:
I found the "anon" customer comments interesting. I would welcome a discussion with anyone regarding Mentor Graphics Customer Support. I feel we are significantly better than the other EDA companies, and have statistics and comments from customers to back this us.
Mentor Graphics is SCP certified and has won the STAR award 5 times. We also recently won the ASP 10 Best Support Web Site award. The interesting thing about SCP, and the awards, is that you have to use customer reported opinions and system statistics to prove you are doing a good job.
Feel free to contact me any time if you would like to learn more.
Vice President of World Wide Customer Support
Mentor Graphics Corp.
Letter No. 5
I, too, have to make a living in this business and therefore want my comments to be anonymous.
I admit that I have a parochial viewpoint. I've been in EDA sales for about 18 years and I'm concerned about the gap between the customer engineer trying to get a job done and the innovative EDA technologist. I think the customer has to own up to a large part of this.
I found your brief talk with Mr. Tobias very interesting. [EDA Weekly, Feb 9th]
In my opinion, he's getting what he pays for. The big FAM deals that Toshiba, Texas Instruments, Intel, etc. enjoy with Synopsys, Cadence, Mentor Graphics, Magma, etc. are driven strictly by the price tag (3-year TBL rates). There are no provisions in their (the customer's) FAM business model for technology innovation or support. The customer has “de-valued” that.
Furthermore, we now see several of these big customers trying to “limit the number of vendors” they do business with, claiming they can save cost by doing so.
I think they must think, “well, if this small company has a good product, one of our big vendors will eventually buy them and they'll become part of our FAM”.
One “Supply Management” person complained to me in negotiations with me on my product that he bought Simplex before the Cadence acquisition. He told me he had assumed that the Simplex products would automatically be included in his Cadence agreement. He was upset when he learned that Cadence did not want to lower their Simplex prices, and they were not compelled to do so contractually.
Technology innovation is not coming from the “Big 3,” as I like to refer to them. If you look at the history of EDA, the most innovative and revolutionary products have more often than not come from the small start-ups. There are several examples to support this:
- Verilog was not developed by CDS, but acquired from the Gateway Design Automation acquisition.
- HSPICE was not developed by Synopsys, but by Meta-Software.
- Compiled-Verilog was not developed by Cadence or Synopsys even after the Gateway Acquisition.
- Dracula was the only game in town and CDS 'milked' it until ISS came on the scene. CDS has never caught up.
- The list goes on and on.
In a previous job, I showed (proved it through evaluation) a prospective customer an ROI model where if they can save just one design iteration, the tools would pay for themselves. But, even though we proved this on a real project, we could never consummate business with them because they had on hand an abundance of inferior similar tools from a “Big 3” at a 14% TBL rate. The ROI model became superfluous to them and the decision was made to use the cheaper, technologically inferior tool.
Later, their failed first-silicon cost them over a million dollars because of the inferior tool. This is not an isolated example; the larger customers are not investing in superior technology or good support.
Just a quick side note on evaluations - imagine going to your local BMW dealer and saying “I'm interested in buying your top of the line model, but, I need to test drive it for three months, maybe longer, before I can make my decision. And, by the way, please don't have any salespeople call me, but, I will expect superior support during my test drive.”
The customers in this industry have an unparalleled opportunity to exhaustively evaluate tools for extended periods of time before they make a buy decision. They have an opportunity to greatly reduce their risk. So, if they are unhappy with what they get, who's at fault?
Another thing I find interesting about Mr. Tobias' comments (or lack of) is that customers are not willing to make the proper investment in their people to make themselves successful.
Training is a good example - no one wants to pay for it although it can make a huge difference in the ramping up of the productivity curve and learning how to get the best results from the tools. This often results in mis-use of the tool, poor results, and failed products. Coding guidelines are not enforced and so the “un-trained” engineer gets himself into trouble when his design doesn't work. So, the first thing they do is point a finger at the tools company.
From an economic perspective then, what are Mr. Tobias' options:
Debug your design in silicon
Develop your own tools
Continue to buy based on price then complain publicly about poor support
Hold yourself and the vendor accountable, take the initiative to build a “Win-Win” relationship with your vendors.
Take the low-risk decisions you had ample time to make through evaluations and protect your investment (e.g. train/qualify your people, employ good methodologies, enforce engineering disciplines, and offer a willingness to recognize that vendor support is of value.)