Intellitech demonstrates at-speed JTAG based testing of Xilinx Rocket IO and DDR1/DDR2 Memories at International Test Conference

AUSTIN, Texas—(BUSINESS WIRE)—Nov. 10, 2005— Intellitech Corporation,, the technology leader in scan-based configuration, debug and test solutions demonstrated new technology for testing the gigabit SERDES connections of Xilinx FPGAs at their rated speed, up to 10G/second in a multi-PCB system. Also demonstrated was at-speed testing of interconnects from FPGAs to double data rate synchronous dynamic ram or DDR RAM. Both at-speed testing technologies are based on Intellitech's patented Fast Access Controller or FAC. The demonstrations included add-on software to Intellitech's popular Eclipse JTAG toolset, Intellitech's BERT IP for Xilinx Rocket IO and DDR testing IP. At-speed testing picks up where stuck-at fault testing with standard IEEE 1149.1/JTAG tests end. The technology promises to enable customers improve quality in systems using FPGAs with high-speed serial links and high-speed memories. These new members of Intellitech's Test-IP family will enable customers to study eye diagrams, rapidly bring up prototype systems and facilitate system level test during production and system integration.

"Some of these interfaces have been difficult to test for our customers, there isn't boundary-scan available on these pins and pogo-pin tests are not an option at high speed. Due to the speeds of the connections they are susceptible to the affects of noise, cross-talk, poor grounding, jitter and imperfections in the interconnect between the ICs" said CJ Clark, Intellitech CEO and past IEEE 1149.1/JTAG working group chairperson. "These can be difficult to find and isolate without having a solid test strategy in place such as this." "There has been some confusion in the marketplace due to past announcements from vendors testing "high-speed SERDES" with IEEE 1149.6 the standard for testing AC coupled interconnects. IEEE 1149.6 is a wonderful standard, however it is still testing for stuck-at faults, misplaced or mis-valued capacitors; it doesn't test the connections at-speed at all", Clark continued. "We have an early adopter that we are working with now as we finalize the feature sets of the tests. The BERT IP and DDR IP will be available for purchase after the first of the year" Clark added.

About Intellitech

Intellitech's TEST-IP(TM) family provides patented infrastructure IP that enables customers to lower the cost of designing, debugging, producing and maintaining electronic systems. Intellitech's proprietary solutions enable customers to build self-testable and in-the-field re-configurable products with the least amount of engineering resources and at the lowest cost. Intellitech lowers production costs by embedding test or enabling concurrent test of electronic assemblies during production test and burn-in. The unified test and configuration approach enables customers to lower manufacturing test costs, provide field adaptable products and retard product obsolescence with field upgrade-able logic.

Kareen Lefoley, 603-868-7116x106
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Review Article
  • October 09, 2008
    Reviewed by 'chen'
    Is this possible? I thought JTAG is slow? It is 5 stars if they can do it. We need Rockets IO test and DDR2 test on Xylinx.

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