The Business of DFM

Design for manufacturing is a messy business, at least for now, but that's what makes it interesting. Now if we could just make it profitable, as well … and that's what this whole column is about.

Because as much as you and I know that technologists are so interested in DFM, they lay awake at night pondering the difficult physics and engineering of designing things to be supremely manufacturable, what really adds merit and oomph to all of their native curiosity and insomnia is, "Yeah, and can I make money on the solutions I come up with? And will I beat everybody else to the punch?"

This column started back in February at DesignCon in Santa Clara. Canaccord Adams hosted a panel called, "The Business of DFM." The panel was moderated by Dennis Wassung, and the panelists included Riko Radojcic from Qualcomm, Ed Wan from TSMC, Jean-Marie Brunet from Mentor Graphics, Jim Wiley from Brion Technologies, Thomas Blaisi from SIGMA-C, and Yervant Zorian from Virage Logic. The questions under discussion here in EDA Weekly arose from that February panel, and include responses from three of the six panelists, plus Mentor Graphics' Joe Sawicki subbing for Jean-Marie Brunet.

Joe and I spoke by phone several weeks ago, because he saw my questions for Jean-Marie, and wanted to walk me through some slides he had used earlier in June at a different Canaccord Adams event -- an all-day series of panels in San Francisco, which also addressed the business of DFM.

One of Joe's slides attempted to lay out the current landscape of DFM -- at least from Mentor Graphics' point of view -- so I decided to expand the scope of this column by submitting my questions to all 14 companies on Joe's slide. I heard back from 10 of them, plus a few other companies as well.

So, go get that tall, extra hot, non-fat, with-whip, grande, double-shot, white mocha. This column -- this "virtual panel" on the business of DFM -- is (groan) over 9000 words long and includes feedback from 15 different companies. The “panelists” include:

Jacob Jacobsson, CEO, Blaze DFM
Atul Sharan, President and CEO, Clear Shape
Chenmin Hu, President, Anchor Semiconductor
Dale Pollek, President & CEO, ChipMD
David Thon, Group Product Marketing Director, DFM, Cadence Design Systems
Dwayne Burek, Senior Director, Design Implementation, Magma Design
Joe Sawicki, Vice President & GM, Design-to-Silicon Division, Mentor Graphics
Mike Gianfagna, President & CEO, Aprio Technologies
Naeem Zafar, President & CEO, Pyxis Technology
Nitin Deo, Sr. Vice President, Marketing & Business Development, Ponte Solutions
Riko Radojcic, Leader of the DFM Initiative, Qualcomm
Rob Aitken, ARM Fellow, ARM
Thomas Blaesi, VP of Marketing & Business Development, SIGMA-C
Srinivas Raghvendra, Senior Director of DFM Solutions, Synopsys
Won-Young Jung, CTO & Executive Vice President, Nanno SOLUTIONS
Yervant Zorian, Vice President & Chief Scientist, Virage Logic

When you're done reading and if you find yourself completely addicted to this stuff (the business of DFM, not caffeine), this is your lucky month! Because there's more where this came from in the shape of a panel happening during the last hour of the last day of the Design Automation Conference in San Francisco, “DFM: Where's the Proof of Value?”

Per the organizers: “The aim of this DAC panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results will be cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement). The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals.”

The moderator is Joe Brandenburg, and the panelists include Jacob Jacobsson, Atul Sharan, Joe Sawicki, Naeem Zafar, and Synopsys' Raul Camposano. This promises to be a fascinating hour and an appropriate end-point for DAC 2006. You should plan to attend. It's happening at 4:30 PM on Thursday, July 27th. Hope to see you there!

[Editor's note: If you weren't included in the (thanks to “EDA John”) now-infamous Buzz@DAC.2006 Part 1 here in EDA Weekly , please send me your or your company's 100-word commentary on what you think will be hot at DAC in San Francisco. I need to hear from you by July 12, 2006.]

The Business of DFM …

1) If you're making money in the DFM market, briefly tell me what technology you're selling. Please be succinct. I'm easily confused here (not kidding!).

Jacob Jacobsson, Blaze DFM -- Blaze is receiving orders for our initial “Electrical DFM” product -- Blaze MO. Blaze MO which was announced in May and is available today as a production release, transforms power and timing requirements into manufacturing directives that optimize the manufacturing process for each individual design. The main benefits are lower leakage power and leakage variability resulting in substantial double-digit gains in parametric yield.

Atul Sharan, Clear Shape -- Clear Shape provides technology that accounts for the impact of systematic variation on design. What designers draw and model -- the ideal -- is NOT what is seen on silicon at sub-100 nanometers. These systematic variations are predictable, and the impact is large enough to cause catastrophic failures such as opens and shorts, also called yield "hot spots." Addressing systematic variations requires too many new rules for rule-based DRC to be sufficient on its own. Additionally, post-GDSII OPC is too slow and occurs too late in the process to be useful to designers.

Clear Shape provides model-based DFM tools which have the requisite speed and accuracy to allow designers to identify manufacturing problems up front in the design cycle -- for example, yield hot spots and impact on electrical parameters such as timing, signal integrity and leakage power -- so that they can do silicon-accurate designs and get the maximum from their process.

Chenmin Hu, Anchor Semiconductor -- As an early start-up in DFM, Anchor has made significant revenue. The first paid customer of Anchor was Xilinx, a fabless design company. That was more than three years ago. The technology is mainly in Lithography Process Check to identify potential hot spots in layout designs.

Dale Pollek, ChipMD -- We provide circuit design (Spice-simulation based) analyses and diagnoses for interactive and automatic circuit optimization of performance and yield. In street terms that means: DesignMD automates tasks, provides a lot more circuit knowledge in less time to make the engineer a lot more intelligent so the designer can make smarter decisions (or use automated decisions as desired) in less time to market netting much better (more robust) circuits (i.e., less time to more market share and profits).

We provide one of the only “design for” solutions that is literally aimed at the high-cost/risk engineer level “design” stage of the flow. Not post layout tooling or drafting stuff that certainly helps make a design to improve manufacturability, that stuff certainly is important, but there is just not really much “designing” at that stage anymore, is there? Most of what I've seen called DFM should really be categorized as LIMA -- Layout, Implementation, Manufacturing, or Autopsy of dead silicon.

1 | 2 | 3 | 4 | 5 | 6 | 7 | 8  Next Page »

Review Article
  • October 09, 2008
    Reviewed by 'Ronald'
    I've been following Peggy's article for more than three years. It is always fresh and informative. This article gives you a quick history (see NTI section) and future vision (see OPC/RET section).

      Was this review helpful to you?   (Report this review as inappropriate)

  • October 09, 2008
    Reviewed by 'Ronald'
    I've been following Peggy's article for more than three years. It is always fresh and informative. This article gives you a quick history (see NTI section) and future vision (see OPC/RET section).

      Was this review helpful to you?   (Report this review as inappropriate)

For more discussions, follow this link …

Latest Blog Posts
Michelle Mata-ReyesAldec Design and Verification
by Michelle Mata-Reyes
ARM-based SoC Co-Emulation using Zynq Boards
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Senior Software Architect Internet for EDA Careers at San Jose, California
Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
Sr. Application Engineer for Mentor Graphics at Fremont, California
Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
Upcoming Events
DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 22 - 26, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise